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Commit 27c5b17c authored Mar 06, 2015 by Brian Norris

mtd: nand: add NAND driver "library" for Broadcom STB NAND controller



This core originated in Set-Top Box chips (BCM7xxx) but is used in a
variety of other Broadcom chips, including some BCM63xxx, BCM33xx, and
iProc/Cygnus. It's been used only on ARM and MIPS SoCs, so restrict it
to those architectures.

There are multiple revisions of this core throughout the years, and
almost every version broke register compatibility in some small way, but
with some effort, this driver is able to support v4.0, v5.0, v6.x, v7.0,
and v7.1. It's been tested on v5.0, v6.0, v6.1, v7.0, and v7.1 recently,
so there hopefully are no more lurking inconsistencies.

This patch adds just some library support, on which platform drivers can
be built.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Tested-by: Florian Fainelli <f.fainelli@gmail.com>

parent bd1b40fe

drivers/mtd/nand/Kconfig

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -394,6 +394,14 @@ config MTD_NAND_GPMI_NAND
	block, such as SD card. So pay attention to it when you enable		block, such as SD card. So pay attention to it when you enable
	the GPMI.		the GPMI.

			config MTD_NAND_BRCMNAND
			tristate "Broadcom STB NAND controller"
			depends on ARM \|\| MIPS
			help
			Enables the Broadcom NAND controller driver. The controller was
			originally designed for Set-Top Box but is used on various BCM7xxx,
			BCM3xxx, BCM63xxx, iProc/Cygnus and more.

	config MTD_NAND_BCM47XXNFLASH		config MTD_NAND_BCM47XXNFLASH
	tristate "Support for NAND flash on BCM4706 BCMA bus"		tristate "Support for NAND flash on BCM4706 BCMA bus"
	depends on BCMA_NFLASH		depends on BCMA_NFLASH

drivers/mtd/nand/Makefile

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -52,5 +52,6 @@ obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
	obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/		obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
	obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o		obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
	obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o		obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
			obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/

	nand-objs := nand_base.o nand_bbt.o nand_timings.o		nand-objs := nand_base.o nand_bbt.o nand_timings.o

drivers/mtd/nand/brcmnand/Makefile

0 → 100644

+1 −0

Original line number	Original line	Diff line number	Diff line
			obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand.o

drivers/mtd/nand/brcmnand/brcmnand.c

0 → 100644

+2195 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/mtd/nand/brcmnand/brcmnand.h

0 → 100644

+58 −0

Original line number	Original line	Diff line number	Diff line
			/*
			* Copyright © 2015 Broadcom Corporation
			*
			* This program is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License version 2 as
			* published by the Free Software Foundation.
			*
			* This program is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*/

			#ifndef __BRCMNAND_H__
			#define __BRCMNAND_H__

			#include <linux/types.h>
			#include <linux/io.h>

			struct platform_device;
			struct dev_pm_ops;

			struct brcmnand_soc {
			struct platform_device *pdev;
			void *priv;
			};

			static inline u32 brcmnand_readl(void __iomem *addr)
			{
			/*
			* MIPS endianness is configured by boot strap, which also reverses all
			* bus endianness (i.e., big-endian CPU + big endian bus ==> native
			* endian I/O).
			*
			* Other architectures (e.g., ARM) either do not support big endian, or
			* else leave I/O in little endian mode.
			*/
			if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(__BIG_ENDIAN))
			return __raw_readl(addr);
			else
			return readl_relaxed(addr);
			}

			static inline void brcmnand_writel(u32 val, void __iomem *addr)
			{
			/* See brcmnand_readl() comments */
			if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(__BIG_ENDIAN))
			__raw_writel(val, addr);
			else
			writel_relaxed(val, addr);
			}

			int brcmnand_probe(struct platform_device pdev, struct brcmnand_soc soc);
			int brcmnand_remove(struct platform_device *pdev);

			extern const struct dev_pm_ops brcmnand_pm_ops;

			#endif /* __BRCMNAND_H__ */