Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 235b87af authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge remote branch 'nouveau/drm-nouveau-next' of ../drm-nouveau-next into drm-core-next 

* 'nouveau/drm-nouveau-next' of ../drm-nouveau-next:
  drm/nouveau: fix __nouveau_fence_wait performance
  drm/nv40: attempt to reserve just enough vram for all 32 channels
  drm/nv50: check for vm traps on every gr irq
  drm/nv50: decode vm faults some more
  drm/nouveau: add nouveau_enum_find() util function
  drm/nouveau: properly handle pushbuffer check failures
  drm/nvc0: remove vm hack forcing large/small pages to not share a PDE
parents bcd5023c bd35fe5a

drivers/gpu/drm/nouveau/nouveau_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -1076,7 +1076,7 @@ extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); 
/* nv50_fb.c */

extern int  nv50_fb_init(struct drm_device *);

extern void nv50_fb_takedown(struct drm_device *);

extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);

extern void nv50_fb_vm_trap(struct drm_device *, int display);



/* nvc0_fb.c */

extern int  nvc0_fb_init(struct drm_device *);

drivers/gpu/drm/nouveau/nouveau_fence.c

+12 −3
Original line number Diff line number Diff line
@@ -27,6 +27,9 @@ 
#include "drmP.h"

#include "drm.h"



#include <linux/ktime.h>

#include <linux/hrtimer.h>



#include "nouveau_drv.h"

#include "nouveau_ramht.h"

#include "nouveau_dma.h"
@@ -229,7 +232,8 @@ int 
__nouveau_fence_wait(void *sync_obj, void *sync_arg, bool lazy, bool intr)

{

	unsigned long timeout = jiffies + (3 * DRM_HZ);

	unsigned long sleep_time = jiffies + 1;

	unsigned long sleep_time = NSEC_PER_MSEC / 1000;

	ktime_t t;

	int ret = 0;



	while (1) {
@@ -243,8 +247,13 @@ __nouveau_fence_wait(void *sync_obj, void *sync_arg, bool lazy, bool intr) 


		__set_current_state(intr ? TASK_INTERRUPTIBLE

			: TASK_UNINTERRUPTIBLE);

		if (lazy && time_after_eq(jiffies, sleep_time))

			schedule_timeout(1);

		if (lazy) {

			t = ktime_set(0, sleep_time);

			schedule_hrtimeout(&t, HRTIMER_MODE_REL);

			sleep_time *= 2;

			if (sleep_time > NSEC_PER_MSEC)

				sleep_time = NSEC_PER_MSEC;

		}



		if (intr && signal_pending(current)) {

			ret = -ERESTARTSYS;

drivers/gpu/drm/nouveau/nouveau_gem.c

+4 −2
Original line number Diff line number Diff line
@@ -600,7 +600,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, 
		if (push[i].bo_index >= req->nr_buffers) {

			NV_ERROR(dev, "push %d buffer not in list\n", i);

			ret = -EINVAL;

			goto out;

			goto out_prevalid;

		}



		bo[push[i].bo_index].read_domains |= (1 << 31);
@@ -612,7 +612,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, 
	if (ret) {

		if (ret != -ERESTARTSYS)

			NV_ERROR(dev, "validate: %d\n", ret);

		goto out;

		goto out_prevalid;

	}



	/* Apply any relocations that are required */
@@ -705,6 +705,8 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, 
out:

	validate_fini(&op, fence);

	nouveau_fence_unref(&fence);



out_prevalid:

	kfree(bo);

	kfree(push);

drivers/gpu/drm/nouveau/nouveau_mem.c

+26 −8
Original line number Diff line number Diff line
@@ -424,14 +424,32 @@ nouveau_mem_vram_init(struct drm_device *dev) 
	}



	/* reserve space at end of VRAM for PRAMIN */

	if (dev_priv->chipset == 0x40 || dev_priv->chipset == 0x47 ||

	    dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b)

		dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024);

	else

	if (dev_priv->card_type >= NV_40)

		dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024);

	else

		dev_priv->ramin_rsvd_vram = (512 * 1024);

	if (dev_priv->card_type >= NV_50) {

		dev_priv->ramin_rsvd_vram = 1 * 1024 * 1024;

	} else

	if (dev_priv->card_type >= NV_40) {

		u32 vs = hweight8((nv_rd32(dev, 0x001540) & 0x0000ff00) >> 8);

		u32 rsvd;



		/* estimate grctx size, the magics come from nv40_grctx.c */

		if      (dev_priv->chipset == 0x40) rsvd = 0x6aa0 * vs;

		else if (dev_priv->chipset  < 0x43) rsvd = 0x4f00 * vs;

		else if (nv44_graph_class(dev))	    rsvd = 0x4980 * vs;

		else				    rsvd = 0x4a40 * vs;

		rsvd += 16 * 1024;

		rsvd *= dev_priv->engine.fifo.channels;



		/* pciegart table */

		if (drm_pci_device_is_pcie(dev))

			rsvd += 512 * 1024;



		/* object storage */

		rsvd += 512 * 1024;



		dev_priv->ramin_rsvd_vram = round_up(rsvd, 4096);

	} else {

		dev_priv->ramin_rsvd_vram = 512 * 1024;

	}



	ret = dev_priv->engine.vram.init(dev);

	if (ret)

drivers/gpu/drm/nouveau/nouveau_sgdma.c

+1 −2
Original line number Diff line number Diff line
@@ -427,8 +427,7 @@ nouveau_sgdma_init(struct drm_device *dev) 
	u32 aper_size, align;

	int ret;



	if (dev_priv->card_type >= NV_50 ||

	    dev_priv->ramin_rsvd_vram >= 2 * 1024 * 1024)

	if (dev_priv->card_type >= NV_50 || drm_pci_device_is_pcie(dev))

		aper_size = 512 * 1024 * 1024;

	else

		aper_size = 64 * 1024 * 1024;