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Commit 1fd2a850 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm/radeon/kms: fix channel_remap setup (v2)
  drm/radeon: Set cursor x/y to 0 when x/yorigin > 0.
  drm/radeon: Update AVIVO cursor coordinate origin before x/yorigin calculation.
  drm/radeon: Simplify cursor x/yorigin calculation.
  drm/radeon/kms: fix cursor image off-by-one error
  drm/radeon/kms: Fix logic error in DP HPD handler
  drm/radeon/kms: add retry limits for native DP aux defer
  drm/radeon/kms: fix regression in DP aux defer handling
parents f8451c3f 12d5180b

drivers/gpu/drm/radeon/atombios_dp.c

+10 −6
Original line number Diff line number Diff line
@@ -115,6 +115,7 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, 
	u8 msg[20];

	int msg_bytes = send_bytes + 4;

	u8 ack;

	unsigned retry;



	if (send_bytes > 16)

		return -1;
@@ -125,20 +126,20 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, 
	msg[3] = (msg_bytes << 4) | (send_bytes - 1);

	memcpy(&msg[4], send, send_bytes);



	while (1) {

	for (retry = 0; retry < 4; retry++) {

		ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,

					    msg, msg_bytes, NULL, 0, delay, &ack);

		if (ret < 0)

			return ret;

		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)

			break;

			return send_bytes;

		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)

			udelay(400);

		else

			return -EIO;

	}



	return send_bytes;

	return -EIO;

}



static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
@@ -149,26 +150,29 @@ static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, 
	int msg_bytes = 4;

	u8 ack;

	int ret;

	unsigned retry;



	msg[0] = address;

	msg[1] = address >> 8;

	msg[2] = AUX_NATIVE_READ << 4;

	msg[3] = (msg_bytes << 4) | (recv_bytes - 1);



	while (1) {

	for (retry = 0; retry < 4; retry++) {

		ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,

					    msg, msg_bytes, recv, recv_bytes, delay, &ack);

		if (ret == 0)

			return -EPROTO;

		if (ret < 0)

			return ret;

		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)

			return ret;

		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)

			udelay(400);

		else if (ret == 0)

			return -EPROTO;

		else

			return -EIO;

	}



	return -EIO;

}



static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,

drivers/gpu/drm/radeon/evergreen.c

+0 −44
Original line number Diff line number Diff line
@@ -1590,48 +1590,6 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 
	return backend_map;

}



static void evergreen_program_channel_remap(struct radeon_device *rdev)

{

	u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;



	tmp = RREG32(MC_SHARED_CHMAP);

	switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {

	case 0:

	case 1:

	case 2:

	case 3:

	default:

		/* default mapping */

		mc_shared_chremap = 0x00fac688;

		break;

	}



	switch (rdev->family) {

	case CHIP_HEMLOCK:

	case CHIP_CYPRESS:

	case CHIP_BARTS:

		tcp_chan_steer_lo = 0x54763210;

		tcp_chan_steer_hi = 0x0000ba98;

		break;

	case CHIP_JUNIPER:

	case CHIP_REDWOOD:

	case CHIP_CEDAR:

	case CHIP_PALM:

	case CHIP_SUMO:

	case CHIP_SUMO2:

	case CHIP_TURKS:

	case CHIP_CAICOS:

	default:

		tcp_chan_steer_lo = 0x76543210;

		tcp_chan_steer_hi = 0x0000ba98;

		break;

	}



	WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);

	WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);

	WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);

}



static void evergreen_gpu_init(struct radeon_device *rdev)

{

	u32 cc_rb_backend_disable = 0;
@@ -2078,8 +2036,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

	WREG32(HDP_ADDR_CONFIG, gb_addr_config);



	evergreen_program_channel_remap(rdev);



	num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;

	grbm_gfx_index = INSTANCE_BROADCAST_WRITES;

drivers/gpu/drm/radeon/ni.c

+0 −32
Original line number Diff line number Diff line
@@ -569,36 +569,6 @@ static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 
	return backend_map;

}



static void cayman_program_channel_remap(struct radeon_device *rdev)

{

	u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;



	tmp = RREG32(MC_SHARED_CHMAP);

	switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {

	case 0:

	case 1:

	case 2:

	case 3:

	default:

		/* default mapping */

		mc_shared_chremap = 0x00fac688;

		break;

	}



	switch (rdev->family) {

	case CHIP_CAYMAN:

	default:

		//tcp_chan_steer_lo = 0x54763210

		tcp_chan_steer_lo = 0x76543210;

		tcp_chan_steer_hi = 0x0000ba98;

		break;

	}



	WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);

	WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);

	WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);

}



static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,

					    u32 disable_mask_per_se,

					    u32 max_disable_mask_per_se,
@@ -842,8 +812,6 @@ static void cayman_gpu_init(struct radeon_device *rdev) 
	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

	WREG32(HDP_ADDR_CONFIG, gb_addr_config);



	cayman_program_channel_remap(rdev);



	/* primary versions */

	WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);

	WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);

drivers/gpu/drm/radeon/radeon_connectors.c

+4 −4
Original line number Diff line number Diff line
@@ -68,11 +68,11 @@ void radeon_connector_hotplug(struct drm_connector *connector) 
	if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {

		int saved_dpms = connector->dpms;



		if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) &&

		    radeon_dp_needs_link_train(radeon_connector))

			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);

		else

		/* Only turn off the display it it's physically disconnected */

		if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))

			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);

		else if (radeon_dp_needs_link_train(radeon_connector))

			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);

		connector->dpms = saved_dpms;

	}

}

drivers/gpu/drm/radeon/radeon_cursor.c

+19 −21
Original line number Diff line number Diff line
@@ -208,24 +208,26 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc, 
	int xorigin = 0, yorigin = 0;

	int w = radeon_crtc->cursor_width;



	if (x < 0)

		xorigin = -x + 1;

	if (y < 0)

		yorigin = -y + 1;

	if (xorigin >= CURSOR_WIDTH)

		xorigin = CURSOR_WIDTH - 1;

	if (yorigin >= CURSOR_HEIGHT)

		yorigin = CURSOR_HEIGHT - 1;



	if (ASIC_IS_AVIVO(rdev)) {

		int i = 0;

		struct drm_crtc *crtc_p;



		/* avivo cursor are offset into the total surface */

		x += crtc->x;

		y += crtc->y;

	}

	DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);



	if (x < 0) {

		xorigin = min(-x, CURSOR_WIDTH - 1);

		x = 0;

	}

	if (y < 0) {

		yorigin = min(-y, CURSOR_HEIGHT - 1);

		y = 0;

	}



	if (ASIC_IS_AVIVO(rdev)) {

		int i = 0;

		struct drm_crtc *crtc_p;



		/* avivo cursor image can't end on 128 pixel boundary or

		 * go past the end of the frame if both crtcs are enabled

		 */
@@ -253,16 +255,12 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc, 


	radeon_lock_cursor(crtc, true);

	if (ASIC_IS_DCE4(rdev)) {

		WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset,

		       ((xorigin ? 0 : x) << 16) |

		       (yorigin ? 0 : y));

		WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);

		WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);

		WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,

		       ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));

	} else if (ASIC_IS_AVIVO(rdev)) {

		WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,

			     ((xorigin ? 0 : x) << 16) |

			     (yorigin ? 0 : y));

		WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);

		WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);

		WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,

		       ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
@@ -276,8 +274,8 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc, 
			| yorigin));

		WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,

		       (RADEON_CUR_LOCK

			| ((xorigin ? 0 : x) << 16)

			| (yorigin ? 0 : y)));

			| (x << 16)

			| y));

		/* offset is from DISP(2)_BASE_ADDRESS */

		WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +

								      (yorigin * 256)));