Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

BIN := vrl4

.PHONY: all

all: $(BIN)

.PHONY: clean

clean:

	rm -f *.o $(BIN)

/*

 * vrl4 format generator

 *

 * Copyright (C) 2010 Simon Horman

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

/*

 * usage: vrl4 < zImage > out

 *	  dd if=out of=/dev/sdx bs=512 seek=1 # Write the image to sector 1

 *

 * Reads a zImage from stdin and writes a vrl4 image to stdout.

 * In practice this means writing a padded vrl4 header to stdout followed

 * by the zImage.

 *

 * The padding places the zImage at ALIGN bytes into the output.

 * The vrl4 uses ALIGN + START_BASE as the start_address.

 * This is where the mask ROM will jump to after verifying the header.

 *

 * The header sets copy_size to min(sizeof(zImage), MAX_BOOT_PROG_LEN) + ALIGN.

 * That is, the mask ROM will load the padded header (ALIGN bytes)

 * And then MAX_BOOT_PROG_LEN bytes of the image, or the entire image,

 * whichever is smaller.

 *

 * The zImage is not modified in any way.

 */

#define _BSD_SOURCE

#include <endian.h>

#include <unistd.h>

#include <stdint.h>

#include <stdio.h>

#include <errno.h>

struct hdr {

	uint32_t magic1;

	uint32_t reserved1;

	uint32_t magic2;

	uint32_t reserved2;

	uint16_t copy_size;

	uint16_t boot_options;

	uint32_t reserved3;

	uint32_t start_address;

	uint32_t reserved4;

	uint32_t reserved5;

	char     reserved6[308];

};

#define DECLARE_HDR(h)					\

	struct hdr (h) = {				\

		.magic1 =	htole32(0xea000000),	\

		.reserved1 =	htole32(0x56),		\

		.magic2 =	htole32(0xe59ff008),	\

		.reserved3 =	htole16(0x1) }

/* Align to 512 bytes, the MMCIF sector size */

#define ALIGN_BITS	9

#define ALIGN		(1 << ALIGN_BITS)

#define START_BASE	0xe55b0000

/*

 * With an alignment of 512 the header uses the first sector.

 * There is a 128 sector (64kbyte) limit on the data loaded by the mask ROM.

 * So there are 127 sectors left for the boot programme. But in practice

 * Only a small portion of a zImage is needed, 16 sectors should be more

 * than enough.

 *

 * Note that this sets how much of the zImage is copied by the mask ROM.

 * The entire zImage is present after the header and is loaded

 * by the code in the boot program (which is the first portion of the zImage).

 */

#define	MAX_BOOT_PROG_LEN (16 * 512)

#define ROUND_UP(x)	((x + ALIGN - 1) & ~(ALIGN - 1))

ssize_t do_read(int fd, void *buf, size_t count)

{

	size_t offset = 0;

	ssize_t l;

	while (offset < count) {

		l = read(fd, buf + offset, count - offset);

		if (!l)

			break;

		if (l < 0) {

			if (errno == EAGAIN || errno == EWOULDBLOCK)

				continue;

			perror("read");

			return -1;

		}

		offset += l;

	}

	return offset;

}

ssize_t do_write(int fd, const void *buf, size_t count)

{

	size_t offset = 0;

	ssize_t l;

	while (offset < count) {

		l = write(fd, buf + offset, count - offset);

		if (l < 0) {

			if (errno == EAGAIN || errno == EWOULDBLOCK)

				continue;

			perror("write");

			return -1;

		}

		offset += l;

	}

	return offset;

}

ssize_t write_zero(int fd, size_t len)

{

	size_t i = len;

	while (i--) {

		const char x = 0;

		if (do_write(fd, &x, 1) < 0)

			return -1;

	}

	return len;

}

int main(void)

{

	DECLARE_HDR(hdr);

	char boot_program[MAX_BOOT_PROG_LEN];

	size_t aligned_hdr_len, alligned_prog_len;

	ssize_t prog_len;

	prog_len = do_read(0, boot_program, sizeof(boot_program));

	if (prog_len <= 0)

		return -1;

	aligned_hdr_len = ROUND_UP(sizeof(hdr));

	hdr.start_address = htole32(START_BASE + aligned_hdr_len);

	alligned_prog_len = ROUND_UP(prog_len);

	hdr.copy_size = htole16(aligned_hdr_len + alligned_prog_len);

	if (do_write(1, &hdr, sizeof(hdr)) < 0)

		return -1;

	if (write_zero(1, aligned_hdr_len - sizeof(hdr)) < 0)

		return -1;

	if (do_write(1, boot_program, prog_len) < 0)

		return 1;

	/* Write out the rest of the kernel */

	while (1) {

		prog_len = do_read(0, boot_program, sizeof(boot_program));

		if (prog_len < 0)

			return 1;

		if (prog_len == 0)

			break;

		if (do_write(1, boot_program, prog_len) < 0)

			return 1;

	}

	return 0;

}

ROM-able zImage boot from MMC

-----------------------------

An ROM-able zImage compiled with ZBOOT_ROM_MMCIF may be written to MMC and

SuperH Mobile ARM will to boot directly from the MMCIF hardware block.

This is achieved by the mask ROM loading the first portion of the image into

MERAM and then jumping to it. This portion contains loader code which

copies the entire image to SDRAM and jumps to it. From there the zImage

boot code proceeds as normal, uncompressing the image into its final

location and then jumping to it.

This code has been tested on an AP4EB board using the developer 1A eMMC

boot mode which is configured using the following jumper settings.

The board used for testing required a patched mask ROM in order for

this mode to function.

   8 7 6 5 4 3 2 1

   x|x|x|x|x| |x|

S4 -+-+-+-+-+-+-+-

    | | | | |x| |x on

The zImage must be written to the MMC card at sector 1 (512 bytes) in

vrl4 format. A utility vrl4 is supplied to accomplish this.

e.g.

	vrl4 < zImage | dd of=/dev/sdX bs=512 seek=1

A dual-voltage MMC 4.0 card was used for testing.

	select HAVE_MEMBLOCK

	select RTC_LIB

	select SYS_SUPPORTS_APM_EMULATION

	select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)

	select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)

	select HAVE_OPROFILE if (HAVE_PERF_EVENTS)

	select HAVE_ARCH_KGDB

	select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)

	select HAVE_PERF_EVENTS

	select PERF_USE_VMALLOC

	select HAVE_REGS_AND_STACK_ACCESS_API

	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))

	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))

	select HAVE_C_RECORDMCOUNT

	select HAVE_GENERIC_HARDIRQS

	select HAVE_SPARSE_IRQ

	depends on GENERIC_CLOCKEVENTS

	default y if SMP

config KTIME_SCALAR

	bool

	default y

config HAVE_TCM

	bool

	select GENERIC_ALLOCATOR

config ARCH_MTD_XIP

	bool

config ARM_L1_CACHE_SHIFT_6

	bool

	help

	  Setting ARM L1 cache line size to 64 Bytes.

config VECTORS_BASE

	hex

	default 0xffff0000 if MMU || CPU_HIGH_VECTOR

	help

	  The base address of exception vectors.

config ARM_PATCH_PHYS_VIRT

	bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"

	depends on EXPERIMENTAL

	depends on !XIP_KERNEL && MMU

	depends on !ARCH_REALVIEW || !SPARSEMEM

	help

	  Patch phys-to-virt translation functions at runtime according to

	  the position of the kernel in system memory.

	  This can only be used with non-XIP with MMU kernels where

	  the base of physical memory is at a 16MB boundary.

config ARM_PATCH_PHYS_VIRT_16BIT

	def_bool y

	depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM

source "init/Kconfig"

source "kernel/Kconfig.freezer"

	bool "FootBridge"

	select CPU_SA110

	select FOOTBRIDGE

	select ARCH_USES_GETTIMEOFFSET

	select GENERIC_CLOCKEVENTS

	help

	  Support for systems based on the DC21285 companion chip

	  ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.

config ARCH_DOVE

	bool "Marvell Dove"

	select CPU_V6K

	select PCI

	select ARCH_REQUIRE_GPIOLIB

	select GENERIC_CLOCKEVENTS

	help

	  Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).

config ARCH_VT8500

	bool "VIA/WonderMedia 85xx"

	select CPU_ARM926T

	select GENERIC_GPIO

	select ARCH_HAS_CPUFREQ

	select GENERIC_CLOCKEVENTS

	select ARCH_REQUIRE_GPIOLIB

	select HAVE_PWM

	help

	  Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.

endchoice

#

source "arch/arm/mach-vexpress/Kconfig"

source "arch/arm/mach-vt8500/Kconfig"

source "arch/arm/mach-w90x900/Kconfig"

# Definitions to make life easier

	default y

config CPU_HAS_PMU

	depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \

	depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \

		   (!ARCH_OMAP3 || OMAP3_EMU)

	default y

	bool

config ARM_ERRATA_411920

	bool "ARM errata: Invalidation of the Instruction Cache operation can fail"

	depends on CPU_V6

	depends on CPU_V6 || CPU_V6K

	help

	  Invalidation of the Instruction Cache operation can

	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.

config PL310_ERRATA_588369

	bool "Clean & Invalidate maintenance operations do not invalidate clean lines"

	depends on CACHE_L2X0 && ARCH_OMAP4

	depends on CACHE_L2X0

	help

	   The PL310 L2 cache controller implements three types of Clean &

	   Invalidate maintenance operations: by Physical Address

	   clean operation followed immediately by an invalidate operation,

	   both performing to the same memory location. This functionality

	   is not correctly implemented in PL310 as clean lines are not

	   invalidated as a result of these operations. Note that this errata

	   uses Texas Instrument's secure monitor api.

	   invalidated as a result of these operations.

config ARM_ERRATA_720789

	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"

	  tables. The workaround changes the TLB flushing routines to invalidate

	  entries regardless of the ASID.

config PL310_ERRATA_727915

	bool "Background Clean & Invalidate by Way operation can cause data corruption"

	depends on CACHE_L2X0

	help

	  PL310 implements the Clean & Invalidate by Way L2 cache maintenance

	  operation (offset 0x7FC). This operation runs in background so that

	  PL310 can handle normal accesses while it is in progress. Under very

	  rare circumstances, due to this erratum, write data can be lost when

	  PL310 treats a cacheable write transaction during a Clean &

	  Invalidate by Way operation.

config ARM_ERRATA_743622

	bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"

	depends on CPU_V7

	  This has the same effect as the cache sync operation: store buffer

	  drain and waiting for all buffers empty.

config ARM_ERRATA_754322

	bool "ARM errata: possible faulty MMU translations following an ASID switch"

	depends on CPU_V7

	help

	  This option enables the workaround for the 754322 Cortex-A9 (r2p*,

	  r3p*) erratum. A speculative memory access may cause a page table walk

	  which starts prior to an ASID switch but completes afterwards. This

	  can populate the micro-TLB with a stale entry which may be hit with

	  the new ASID. This workaround places two dsb instructions in the mm

	  switching code so that no page table walks can cross the ASID switch.

config ARM_ERRATA_754327

	bool "ARM errata: no automatic Store Buffer drain"

	depends on CPU_V7 && SMP

	help

	  This option enables the workaround for the 754327 Cortex-A9 (prior to

	  r2p0) erratum. The Store Buffer does not have any automatic draining

	  mechanism and therefore a livelock may occur if an external agent

	  continuously polls a memory location waiting to observe an update.

	  This workaround defines cpu_relax() as smp_mb(), preventing correctly

	  written polling loops from denying visibility of updates to memory.

endmenu

source "arch/arm/common/Kconfig"

config SMP

	bool "Symmetric Multi-Processing (EXPERIMENTAL)"

	depends on EXPERIMENTAL

	depends on CPU_V6K || CPU_V7

	depends on GENERIC_CLOCKEVENTS

	depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \

		 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \

config THUMB2_KERNEL

	bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"

	depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL

	depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL

	select AEABI

	select ARM_ASM_UNIFIED

	help

	  If unsure, say N.

config THUMB2_AVOID_R_ARM_THM_JUMP11

	bool "Work around buggy Thumb-2 short branch relocations in gas"

	depends on THUMB2_KERNEL && MODULES

	default y

	help

	  Various binutils versions can resolve Thumb-2 branches to

	  locally-defined, preemptible global symbols as short-range "b.n"

	  branch instructions.

	  This is a problem, because there's no guarantee the final

	  destination of the symbol, or any candidate locations for a

	  trampoline, are within range of the branch.  For this reason, the

	  kernel does not support fixing up the R_ARM_THM_JUMP11 (102)

	  relocation in modules at all, and it makes little sense to add

	  support.

	  The symptom is that the kernel fails with an "unsupported

	  relocation" error when loading some modules.

	  Until fixed tools are available, passing

	  -fno-optimize-sibling-calls to gcc should prevent gcc generating

	  code which hits this problem, at the cost of a bit of extra runtime

	  stack usage in some cases.

	  The problem is described in more detail at:

	      https://bugs.launchpad.net/binutils-linaro/+bug/725126

	  Only Thumb-2 kernels are affected.

	  Unless you are sure your tools don't have this problem, say Y.

config ARM_ASM_UNIFIED

	bool

	  Say Y here if you intend to execute your compressed kernel image

	  (zImage) directly from ROM or flash.  If unsure, say N.

config ZBOOT_ROM_MMCIF

	bool "Include MMCIF loader in zImage (EXPERIMENTAL)"

	depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL

	help

	  Say Y here to include experimental MMCIF loading code in the

	  ROM-able zImage. With this enabled it is possible to write the

	  the ROM-able zImage kernel image to an MMC card and boot the

	  kernel straight from the reset vector. At reset the processor

	  Mask ROM will load the first part of the the ROM-able zImage

	  which in turn loads the rest the kernel image to RAM using the

	  MMCIF hardware block.

config CMDLINE

	string "Default kernel command string"

	default ""

config VFP

	bool "VFP-format floating point maths"

	depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON

	depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON

	help

	  Say Y to include VFP support code in the kernel. This is needed

	  if your hardware includes a VFP unit.

tune-$(CONFIG_CPU_XSC3)		:=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale

tune-$(CONFIG_CPU_FEROCEON)	:=$(call cc-option,-mtune=marvell-f,-mtune=xscale)

tune-$(CONFIG_CPU_V6)		:=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)

tune-$(CONFIG_CPU_V6K)		:=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)

ifeq ($(CONFIG_AEABI),y)

CFLAGS_ABI	:=-mabi=aapcs-linux -mno-thumb-interwork

AFLAGS_NOWARN	:=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W)

CFLAGS_THUMB2	:=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN)

AFLAGS_THUMB2	:=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb

# Work around buggy relocation from gas if requested:

ifeq ($(CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11),y)

CFLAGS_MODULE	+=-fno-optimize-sibling-calls

endif

endif

# Need -Uarm for gcc < 3.x

machine-$(CONFIG_ARCH_U8500)		:= ux500

machine-$(CONFIG_ARCH_VERSATILE)	:= versatile

machine-$(CONFIG_ARCH_VEXPRESS)		:= vexpress

machine-$(CONFIG_ARCH_VT8500)		:= vt8500

machine-$(CONFIG_ARCH_W90X900)		:= w90x900

machine-$(CONFIG_ARCH_NUC93X)		:= nuc93x

machine-$(CONFIG_FOOTBRIDGE)		:= footbridge

zImage Image xipImage bootpImage uImage: vmlinux

	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@

zinstall install: vmlinux

zinstall uinstall install: vmlinux

	$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@

# We use MRPROPER_FILES and CLEAN_FILES now

  echo  '                  (supply initrd image via make variable INITRD=<path>)'

  echo  '  install       - Install uncompressed kernel'

  echo  '  zinstall      - Install compressed kernel'

  echo  '  uinstall      - Install U-Boot wrapped compressed kernel'

  echo  '                  Install using (your) ~/bin/$(INSTALLKERNEL) or'

  echo  '                  (distribution) /sbin/$(INSTALLKERNEL) or'

  echo  '                  install to $$(INSTALL_PATH) and run lilo'