Commit 15ebb052 authored Jun 19, 2014 by Thomas Gleixner Committed by Mike Turquette Jul 13, 2014

clk: spear3xx: Use proper control register offset



The control register is at offset 0x10, not 0x0. This is wreckaged
since commit 5df33a62 (SPEAr: Switch to common clock framework).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

parent c556bcdd

drivers/clk/spear/spear3xx_clock.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -211,7 +211,7 @@ static inline void spear310_clk_init(void) { }
		/* array of all spear 320 clock lookups */
		#ifdef CONFIG_MACH_SPEAR320

		#define SPEAR320_CONTROL_REG (soc_config_base + 0x0000)
		#define SPEAR320_CONTROL_REG (soc_config_base + 0x0010)
		#define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018)

		#define SPEAR320_UARTX_PCLK_MASK 0x1