ARM: 7461/1: topology: Add arch_scale_freq_power function

#include <asm/cputype.h>

#include <asm/topology.h>

/*

 * cpu power scale management

 */

/*

 * cpu power table

 * This per cpu data structure describes the relative capacity of each core.

 * On a heteregenous system, cores don't have the same computation capacity

 * and we reflect that difference in the cpu_power field so the scheduler can

 * take this difference into account during load balance. A per cpu structure

 * is preferred because each CPU updates its own cpu_power field during the

 * load balance except for idle cores. One idle core is selected to run the

 * rebalance_domains for all idle cores and the cpu_power can be updated

 * during this sequence.

 */

static DEFINE_PER_CPU(unsigned long, cpu_scale);

unsigned long arch_scale_freq_power(struct sched_domain *sd, int cpu)

{

	return per_cpu(cpu_scale, cpu);

}

static void set_power_scale(unsigned int cpu, unsigned long power)

{

	per_cpu(cpu_scale, cpu) = power;

}

/*

 * cpu topology management

 */

#define MPIDR_SMP_BITMASK (0x3 << 30)

#define MPIDR_SMP_VALUE (0x2 << 30)

#define MPIDR_LEVEL2_MASK 0xFF

#define MPIDR_LEVEL2_SHIFT 16

/*

 * cpu topology table

 */

struct cputopo_arm cpu_topology[NR_CPUS];

const struct cpumask *cpu_coregroup_mask(int cpu)

{

	unsigned int cpu;

	/* init core mask */

	/* init core mask and power*/

	for_each_possible_cpu(cpu) {

		struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]);

		cpu_topo->socket_id = -1;

		cpumask_clear(&cpu_topo->core_sibling);

		cpumask_clear(&cpu_topo->thread_sibling);

		set_power_scale(cpu, SCHED_POWER_SCALE);

	}

	smp_wmb();

}