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Commit 0a732870 authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
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drm/i915: BUG_ON bad PPGTT offset 



Because PPGTT PDEs within the GTT are calculated in cachelines
(HW guys consistency ftw) we do a divide which will wreak havoc if this
is wrong, and I know that from experience).

If/when we move to multiple PPGTTs this will have to become a WARN, and
return an error. For now however it should always be considered fatal,
and only a developer could hit it.

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
[danvet: s/BUG/WARN]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 186507e9

drivers/gpu/drm/i915/i915_gem_gtt.c

+2 −0
Original line number Diff line number Diff line
@@ -110,6 +110,8 @@ static int gen6_ppgtt_enable(struct drm_device *dev) 
	uint32_t pd_entry;

	int i;



	WARN_ON(ppgtt->pd_offset & 0x3f);



	pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +

		ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);

	for (i = 0; i < ppgtt->num_pd_entries; i++) {