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Commit 0846c728 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-nouveau-next' of... 

Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next

- Page flipping fixes, with support for syncing them to vblank (finally...).
- Misc other general fixes

* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6:
  drm/nouveau: do not map evicted vram buffers in nouveau_bo_vma_add
  drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800
  drm/nouveau/pwr: fix missing mutex unlock in a failure path
  drm/nv40/therm: fix slowing down fan when pstate undefined
  drm/nv11-: synchronise flips to vblank, unless async flip requested
  drm/nvc0-: remove nasty fifo swmthd hack for flip completion method
  drm/nv10-: we no longer need to create nvsw object on user channels
  drm/nouveau: always queue flips relative to kernel channel activity
  drm/nouveau: there is no need to reserve/fence the new fb when flipping
  drm/nouveau: when bailing out of a pushbuf ioctl, do not remove previous fence
  drm/nouveau: allow nouveau_fence_ref() to be a noop
  drm/nvc8/mc: msi rearm is via the nvc0 method
parents ad40f83f d2c7ab32

drivers/gpu/drm/nouveau/core/engine/device/nvc0.c

+1 −1
Original line number Diff line number Diff line
@@ -256,7 +256,7 @@ nvc0_identify(struct nouveau_device *device) 
		device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;

		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;

		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;

		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc3_mc_oclass;

		device->oclass[NVDEV_SUBDEV_MC     ] =  nvc0_mc_oclass;

		device->oclass[NVDEV_SUBDEV_BUS    ] =  nvc0_bus_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] =  nvc0_fb_oclass;

drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c

+0 −7
Original line number Diff line number Diff line
@@ -494,13 +494,6 @@ nvc0_fifo_isr_subfifo_intr(struct nvc0_fifo_priv *priv, int unit) 
	u32 mthd = (addr & 0x00003ffc);

	u32 show = stat;



	if (stat & 0x00200000) {

		if (mthd == 0x0054) {

			if (!nvc0_fifo_swmthd(priv, chid, 0x0500, 0x00000000))

				show &= ~0x00200000;

		}

	}



	if (stat & 0x00800000) {

		if (!nvc0_fifo_swmthd(priv, chid, mthd, data))

			show &= ~0x00800000;

drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c

+0 −7
Original line number Diff line number Diff line
@@ -481,13 +481,6 @@ nve0_fifo_isr_subfifo_intr(struct nve0_fifo_priv *priv, int unit) 
	u32 mthd = (addr & 0x00003ffc);

	u32 show = stat;



	if (stat & 0x00200000) {

		if (mthd == 0x0054) {

			if (!nve0_fifo_swmthd(priv, chid, 0x0500, 0x00000000))

				show &= ~0x00200000;

		}

	}



	if (stat & 0x00800000) {

		if (!nve0_fifo_swmthd(priv, chid, mthd, data))

			show &= ~0x00800000;

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c

+1 −1
Original line number Diff line number Diff line
@@ -1039,7 +1039,7 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv) 
			} while (!tpcnr[gpc]);

			tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;



			tpc_set |= 1 << ((gpc * 8) + tpc);

			tpc_set |= 1ULL << ((gpc * 8) + tpc);

		}



		nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));

drivers/gpu/drm/nouveau/core/subdev/pwr/base.c

+5 −5
Original line number Diff line number Diff line
@@ -32,6 +32,11 @@ nouveau_pwr_send(struct nouveau_pwr *ppwr, u32 reply[2], 
	struct nouveau_subdev *subdev = nv_subdev(ppwr);

	u32 addr;



	/* wait for a free slot in the fifo */

	addr  = nv_rd32(ppwr, 0x10a4a0);

	if (!nv_wait_ne(ppwr, 0x10a4b0, 0xffffffff, addr ^ 8))

		return -EBUSY;



	/* we currently only support a single process at a time waiting

	 * on a synchronous reply, take the PPWR mutex and tell the

	 * receive handler what we're waiting for
@@ -42,11 +47,6 @@ nouveau_pwr_send(struct nouveau_pwr *ppwr, u32 reply[2], 
		ppwr->recv.process = process;

	}



	/* wait for a free slot in the fifo */

	addr  = nv_rd32(ppwr, 0x10a4a0);

	if (!nv_wait_ne(ppwr, 0x10a4b0, 0xffffffff, addr ^ 8))

		return -EBUSY;



	/* acquire data segment access */

	do {

		nv_wr32(ppwr, 0x10a580, 0x00000001);