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Commit 0835ae0f authored by David S. Miller's avatar David S. Miller
Browse files

[SPARC64]: Replace cheetah+ code patching with variables. 



Instead of code patching to handle the page size fields in
the context registers, just use variables from which we get
the proper values.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent dd7205ed

arch/sparc64/kernel/entry.S

+8 −35
Original line number Diff line number Diff line
@@ -97,8 +97,8 @@ do_fpdis: 
	faddd		%f0, %f2, %f4

	fmuld		%f0, %f2, %f6

	ldxa		[%g3] ASI_DMMU, %g5

cplus_fptrap_insn_1:

	sethi		%hi(0), %g2

	sethi		%hi(sparc64_kern_sec_context), %g2

	ldx		[%g2 + %lo(sparc64_kern_sec_context)], %g2

	stxa		%g2, [%g3] ASI_DMMU

	membar		#Sync

	add		%g6, TI_FPREGS + 0xc0, %g2
@@ -126,8 +126,8 @@ cplus_fptrap_insn_1: 
	fzero		%f34

	ldxa		[%g3] ASI_DMMU, %g5

	add		%g6, TI_FPREGS, %g1

cplus_fptrap_insn_2:

	sethi		%hi(0), %g2

	sethi		%hi(sparc64_kern_sec_context), %g2

	ldx		[%g2 + %lo(sparc64_kern_sec_context)], %g2

	stxa		%g2, [%g3] ASI_DMMU

	membar		#Sync

	add		%g6, TI_FPREGS + 0x40, %g2
@@ -153,8 +153,8 @@ cplus_fptrap_insn_2: 
3:	mov		SECONDARY_CONTEXT, %g3

	add		%g6, TI_FPREGS, %g1

	ldxa		[%g3] ASI_DMMU, %g5

cplus_fptrap_insn_3:

	sethi		%hi(0), %g2

	sethi		%hi(sparc64_kern_sec_context), %g2

	ldx		[%g2 + %lo(sparc64_kern_sec_context)], %g2

	stxa		%g2, [%g3] ASI_DMMU

	membar		#Sync

	mov		0x40, %g2
@@ -319,8 +319,8 @@ do_fptrap_after_fsr: 
	stx		%g3, [%g6 + TI_GSR]

	mov		SECONDARY_CONTEXT, %g3

	ldxa		[%g3] ASI_DMMU, %g5

cplus_fptrap_insn_4:

	sethi		%hi(0), %g2

	sethi		%hi(sparc64_kern_sec_context), %g2

	ldx		[%g2 + %lo(sparc64_kern_sec_context)], %g2

	stxa		%g2, [%g3] ASI_DMMU

	membar		#Sync

	add		%g6, TI_FPREGS, %g2
@@ -341,33 +341,6 @@ cplus_fptrap_insn_4: 
	ba,pt		%xcc, etrap

	 wr		%g0, 0, %fprs



cplus_fptrap_1:

	sethi		%hi(CTX_CHEETAH_PLUS_CTX0), %g2



	.globl		cheetah_plus_patch_fpdis

cheetah_plus_patch_fpdis:

	/* We configure the dTLB512_0 for 4MB pages and the

	 * dTLB512_1 for 8K pages when in context zero.

	 */

	sethi			%hi(cplus_fptrap_1), %o0

	lduw			[%o0 + %lo(cplus_fptrap_1)], %o1



	set			cplus_fptrap_insn_1, %o2

	stw			%o1, [%o2]

	flush			%o2

	set			cplus_fptrap_insn_2, %o2

	stw			%o1, [%o2]

	flush			%o2

	set			cplus_fptrap_insn_3, %o2

	stw			%o1, [%o2]

	flush			%o2

	set			cplus_fptrap_insn_4, %o2

	stw			%o1, [%o2]

	flush			%o2



	retl

	 nop



	/* The registers for cross calls will be:

	 *

	 * DATA 0: [low 32-bits]  Address of function to call, jmp to this

arch/sparc64/kernel/etrap.S

+4 −47
Original line number Diff line number Diff line
@@ -68,12 +68,8 @@ etrap_irq: 


		wrpr	%g3, 0, %otherwin

		wrpr	%g2, 0, %wstate

cplus_etrap_insn_1:

		sethi	%hi(0), %g3

		sllx	%g3, 32, %g3

cplus_etrap_insn_2:

		sethi	%hi(0), %g2

		or	%g3, %g2, %g3

		sethi	%hi(sparc64_kern_pri_context), %g2

		ldx	[%g2 + %lo(sparc64_kern_pri_context)], %g3

		stxa	%g3, [%l4] ASI_DMMU

		flush	%l6

		wr	%g0, ASI_AIUS, %asi
@@ -215,12 +211,8 @@ scetrap: rdpr %pil, %g2 
		mov	PRIMARY_CONTEXT, %l4

		wrpr	%g3, 0, %otherwin

		wrpr	%g2, 0, %wstate

cplus_etrap_insn_3:

		sethi	%hi(0), %g3

		sllx	%g3, 32, %g3

cplus_etrap_insn_4:

		sethi	%hi(0), %g2

		or	%g3, %g2, %g3

		sethi	%hi(sparc64_kern_pri_context), %g2

		ldx	[%g2 + %lo(sparc64_kern_pri_context)], %g3

		stxa	%g3, [%l4] ASI_DMMU

		flush	%l6
@@ -264,38 +256,3 @@ cplus_etrap_insn_4: 


#undef TASK_REGOFF

#undef ETRAP_PSTATE1
 


cplus_einsn_1:

		sethi			%uhi(CTX_CHEETAH_PLUS_NUC), %g3

cplus_einsn_2:

		sethi			%hi(CTX_CHEETAH_PLUS_CTX0), %g2



		.globl			cheetah_plus_patch_etrap

cheetah_plus_patch_etrap:

		/* We configure the dTLB512_0 for 4MB pages and the

		 * dTLB512_1 for 8K pages when in context zero.

		 */

		sethi			%hi(cplus_einsn_1), %o0

		sethi			%hi(cplus_etrap_insn_1), %o2

		lduw			[%o0 + %lo(cplus_einsn_1)], %o1

		or			%o2, %lo(cplus_etrap_insn_1), %o2

		stw			%o1, [%o2]

		flush			%o2

		sethi			%hi(cplus_etrap_insn_3), %o2

		or			%o2, %lo(cplus_etrap_insn_3), %o2

		stw			%o1, [%o2]

		flush			%o2



		sethi			%hi(cplus_einsn_2), %o0

		sethi			%hi(cplus_etrap_insn_2), %o2

		lduw			[%o0 + %lo(cplus_einsn_2)], %o1

		or			%o2, %lo(cplus_etrap_insn_2), %o2

		stw			%o1, [%o2]

		flush			%o2

		sethi			%hi(cplus_etrap_insn_4), %o2

		or			%o2, %lo(cplus_etrap_insn_4), %o2

		stw			%o1, [%o2]

		flush			%o2



		retl

		 nop

arch/sparc64/kernel/head.S

+5 −28
Original line number Diff line number Diff line
@@ -325,23 +325,7 @@ cheetah_tlb_fixup: 
1:	sethi	%hi(tlb_type), %g1

	stw	%g2, [%g1 + %lo(tlb_type)]



	BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)

	ba,pt	%xcc, 2f

	 nop



1:	/* Patch context register writes to support nucleus page

	 * size correctly.

	 */

	call	cheetah_plus_patch_etrap

	 nop

	call	cheetah_plus_patch_rtrap

	 nop

	call	cheetah_plus_patch_fpdis

	 nop

	call	cheetah_plus_patch_winfixup

	 nop



2:	/* Patch copy/page operations to cheetah optimized versions. */

	/* Patch copy/page operations to cheetah optimized versions. */

	call	cheetah_patch_copyops

	 nop

	call	cheetah_patch_copy_page
@@ -484,20 +468,13 @@ spitfire_vpte_base: 
	call	prom_set_trap_table

	 sethi	%hi(sparc64_ttable_tl0), %o0



	BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g2,g3,1f)

	ba,pt	%xcc, 2f

	 nop



1:	/* Start using proper page size encodings in ctx register.  */

	sethi	%uhi(CTX_CHEETAH_PLUS_NUC), %g3

	/* Start using proper page size encodings in ctx register.  */

	sethi	%hi(sparc64_kern_pri_context), %g3

	ldx	[%g3 + %lo(sparc64_kern_pri_context)], %g2

	mov	PRIMARY_CONTEXT, %g1

	sllx	%g3, 32, %g3

	sethi	%hi(CTX_CHEETAH_PLUS_CTX0), %g2

	or	%g3, %g2, %g3

	stxa	%g3, [%g1] ASI_DMMU

	stxa	%g2, [%g1] ASI_DMMU

	membar	#Sync



2:

	rdpr	%pstate, %o1

	or	%o1, PSTATE_IE, %o1

	wrpr	%o1, 0, %pstate

arch/sparc64/kernel/rtrap.S

+2 −21
Original line number Diff line number Diff line
@@ -256,9 +256,8 @@ rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1 
		brnz,pn			%l3, kern_rtt

		 mov			PRIMARY_CONTEXT, %l7

		ldxa			[%l7 + %l7] ASI_DMMU, %l0

cplus_rtrap_insn_1:

		sethi			%hi(0), %l1

		sllx			%l1, 32, %l1

		sethi			%hi(sparc64_kern_pri_nuc_bits), %l1

		ldx			[%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1

		or			%l0, %l1, %l0

		stxa			%l0, [%l7] ASI_DMMU

		flush			%g6
@@ -345,21 +344,3 @@ kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5 
		wr			%g0, FPRS_DU, %fprs

		ba,pt			%xcc, rt_continue

		 stb			%l5, [%g6 + TI_FPDEPTH]
 


cplus_rinsn_1:

		sethi			%uhi(CTX_CHEETAH_PLUS_NUC), %l1



		.globl			cheetah_plus_patch_rtrap

cheetah_plus_patch_rtrap:

		/* We configure the dTLB512_0 for 4MB pages and the

		 * dTLB512_1 for 8K pages when in context zero.

		 */

		sethi			%hi(cplus_rinsn_1), %o0

		sethi			%hi(cplus_rtrap_insn_1), %o2

		lduw			[%o0 + %lo(cplus_rinsn_1)], %o1

		or			%o2, %lo(cplus_rtrap_insn_1), %o2

		stw			%o1, [%o2]

		flush			%o2



		retl

		 nop

arch/sparc64/kernel/setup.c

+2 −6
Original line number Diff line number Diff line
@@ -187,17 +187,13 @@ int prom_callback(long *args) 
		}



		if ((va >= KERNBASE) && (va < (KERNBASE + (4 * 1024 * 1024)))) {

			unsigned long kernel_pctx = 0;



			if (tlb_type == cheetah_plus)

				kernel_pctx |= (CTX_CHEETAH_PLUS_NUC |

						CTX_CHEETAH_PLUS_CTX0);

			extern unsigned long sparc64_kern_pri_context;



			/* Spitfire Errata #32 workaround */

			__asm__ __volatile__("stxa	%0, [%1] %2\n\t"

					     "flush	%%g6"

					     : /* No outputs */

					     : "r" (kernel_pctx),

					     : "r" (sparc64_kern_pri_context),

					       "r" (PRIMARY_CONTEXT),

					       "i" (ASI_DMMU));