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Commit 04cf7941 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc 

From Sascha Hauer <s.hauer@pengutronix.de>:
ARM i.MX SoC updates for 3.6

* tag 'imx-soc' of git://git.pengutronix.de/git/imx/linux-2.6

:
  ARM: imx: fix mx51 ehci setup errors
  ARM: imx: make ehci power/oc polarities configurable
  ARM: imx: add rtc support to mx35_3ds
  ARM: imx: enable support for mx35 rtc
  ARM: imx: fix i.MX35 CPU architecture
  ARM: i.MX51 iomux: added missing pin definitions

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 0dc19510 0b87c1d4

arch/arm/mach-imx/Kconfig

+2 −1
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ config SOC_IMX31 


config SOC_IMX35

	bool

	select CPU_V6

	select CPU_V6K

	select ARCH_MXC_IOMUX_V3

	select COMMON_CLK

	select HAVE_EPIT
@@ -589,6 +589,7 @@ config MACH_MX35_3DS 
	select IMX_HAVE_PLATFORM_IPU_CORE

	select IMX_HAVE_PLATFORM_MXC_EHCI

	select IMX_HAVE_PLATFORM_MXC_NAND

	select IMX_HAVE_PLATFORM_MXC_RTC

	select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX

	help

	  Include support for MX35PDK platform. This includes specific

arch/arm/mach-imx/devices-imx35.h

+4 −0
Original line number Diff line number Diff line
@@ -68,6 +68,10 @@ extern const struct imx_mxc_nand_data imx35_mxc_nand_data; 
#define imx35_add_mxc_nand(pdata)	\

	imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)



extern const struct imx_mxc_rtc_data imx35_mxc_rtc_data;

#define imx35_add_mxc_rtc()	\

	imx_add_mxc_rtc(&imx35_mxc_rtc_data)



extern const struct imx_mxc_w1_data imx35_mxc_w1_data;

#define imx35_add_mxc_w1(pdata)	\

	imx_add_mxc_w1(&imx35_mxc_w1_data)

arch/arm/mach-imx/ehci-imx25.c

+21 −3
Original line number Diff line number Diff line
@@ -24,14 +24,18 @@ 
#define MX25_OTG_SIC_SHIFT	29

#define MX25_OTG_SIC_MASK	(0x3 << MX25_OTG_SIC_SHIFT)

#define MX25_OTG_PM_BIT		(1 << 24)

#define MX25_OTG_PP_BIT		(1 << 11)

#define MX25_OTG_OCPOL_BIT	(1 << 3)



#define MX25_H1_SIC_SHIFT	21

#define MX25_H1_SIC_MASK	(0x3 << MX25_H1_SIC_SHIFT)

#define MX25_H1_PP_BIT		(1 << 18)

#define MX25_H1_PM_BIT		(1 << 8)

#define MX25_H1_IPPUE_UP_BIT	(1 << 7)

#define MX25_H1_IPPUE_DOWN_BIT	(1 << 6)

#define MX25_H1_TLL_BIT		(1 << 5)

#define MX25_H1_USBTE_BIT	(1 << 4)

#define MX25_H1_OCPOL_BIT	(1 << 2)



int mx25_initialize_usb_hw(int port, unsigned int flags)

{
@@ -41,21 +45,35 @@ int mx25_initialize_usb_hw(int port, unsigned int flags) 


	switch (port) {

	case 0:	/* OTG port */

		v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT);

		v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |

			MX25_OTG_OCPOL_BIT);

		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;



		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))

			v |= MX25_OTG_PM_BIT;



		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)

			v |= MX25_OTG_PP_BIT;



		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))

			v |= MX25_OTG_OCPOL_BIT;



		break;

	case 1: /* H1 port */

		v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_TLL_BIT |

			MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);

		v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |

			MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |

			MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);

		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;



		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))

			v |= MX25_H1_PM_BIT;



		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)

			v |= MX25_H1_PP_BIT;



		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))

			v |= MX25_H1_OCPOL_BIT;



		if (!(flags & MXC_EHCI_TTL_ENABLED))

			v |= MX25_H1_TLL_BIT;

arch/arm/mach-imx/ehci-imx35.c

+21 −3
Original line number Diff line number Diff line
@@ -24,14 +24,18 @@ 
#define MX35_OTG_SIC_SHIFT	29

#define MX35_OTG_SIC_MASK	(0x3 << MX35_OTG_SIC_SHIFT)

#define MX35_OTG_PM_BIT		(1 << 24)

#define MX35_OTG_PP_BIT		(1 << 11)

#define MX35_OTG_OCPOL_BIT	(1 << 3)



#define MX35_H1_SIC_SHIFT	21

#define MX35_H1_SIC_MASK	(0x3 << MX35_H1_SIC_SHIFT)

#define MX35_H1_PP_BIT		(1 << 18)

#define MX35_H1_PM_BIT		(1 << 8)

#define MX35_H1_IPPUE_UP_BIT	(1 << 7)

#define MX35_H1_IPPUE_DOWN_BIT	(1 << 6)

#define MX35_H1_TLL_BIT		(1 << 5)

#define MX35_H1_USBTE_BIT	(1 << 4)

#define MX35_H1_OCPOL_BIT	(1 << 2)



int mx35_initialize_usb_hw(int port, unsigned int flags)

{
@@ -41,21 +45,35 @@ int mx35_initialize_usb_hw(int port, unsigned int flags) 


	switch (port) {

	case 0:	/* OTG port */

		v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);

		v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |

			MX35_OTG_OCPOL_BIT);

		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;



		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))

			v |= MX35_OTG_PM_BIT;



		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)

			v |= MX35_OTG_PP_BIT;



		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))

			v |= MX35_OTG_OCPOL_BIT;



		break;

	case 1: /* H1 port */

		v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |

			MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);

		v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |

			MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |

			MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);

		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;



		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))

			v |= MX35_H1_PM_BIT;



		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)

			v |= MX35_H1_PP_BIT;



		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))

			v |= MX35_H1_OCPOL_BIT;



		if (!(flags & MXC_EHCI_TTL_ENABLED))

			v |= MX35_H1_TLL_BIT;

arch/arm/mach-imx/ehci-imx5.c

+23 −8
Original line number Diff line number Diff line
@@ -31,8 +31,11 @@ 
#define MXC_H1_UCTRL_H1PM_BIT		(1 <<  8)	/* HOST1 power mask */



/* USB_PHY_CTRL_FUNC */

#define MXC_OTG_PHYCTRL_OC_POL_BIT	(1 << 9)	/* OTG Polarity of Overcurrent */

#define MXC_OTG_PHYCTRL_OC_DIS_BIT	(1 << 8)	/* OTG Disable Overcurrent Event */

#define MXC_H1_OC_POL_BIT		(1 << 6)	/* UH1 Polarity of Overcurrent */

#define MXC_H1_OC_DIS_BIT		(1 << 5)	/* UH1 Disable Overcurrent Event */

#define MXC_OTG_PHYCTRL_PWR_POL_BIT	(1 << 3)	/* OTG Power Pin Polarity */



/* USBH2CTRL */

#define MXC_H2_UCTRL_H2UIE_BIT		(1 << 8)
@@ -80,13 +83,21 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) 
		if (flags & MXC_EHCI_INTERNAL_PHY) {

			v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);



			if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)

				v |= MXC_OTG_PHYCTRL_OC_POL_BIT;

			else

				v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;

			if (flags & MXC_EHCI_POWER_PINS_ENABLED) {

				/* OC/USBPWR is not used */

				v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;

			} else {

				/* OC/USBPWR is used */

				v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;

			} else {

				/* OC/USBPWR is not used */

				v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;

			}

			if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)

				v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;

			else

				v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;

			__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);



			v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
@@ -95,9 +106,9 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) 
			else

				v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */

			if (flags & MXC_EHCI_POWER_PINS_ENABLED)

				v |= MXC_OTG_UCTRL_OPM_BIT;

			else

				v &= ~MXC_OTG_UCTRL_OPM_BIT;

			else

				v |= MXC_OTG_UCTRL_OPM_BIT;

			__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);

		}

		break;
@@ -113,12 +124,16 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) 
		}



		if (flags & MXC_EHCI_POWER_PINS_ENABLED)

			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/

			v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/

		else

			v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/

		__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);



		v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);

		if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)

			v |= MXC_H1_OC_POL_BIT;

		else

			v &= ~MXC_H1_OC_POL_BIT;

		if (flags & MXC_EHCI_POWER_PINS_ENABLED)

			v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */

		else
@@ -142,7 +157,7 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) 
		}



		if (flags & MXC_EHCI_POWER_PINS_ENABLED)

			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/

			v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/

		else

			v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/

		__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);