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Commit 01aa2997 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'gmac-next' 



Roger Chen says:

====================
support GMAC driver for RK3288

Roger Chen (6):
  patch1: add driver for Rockchip RK3288 SoCs integrated GMAC
  patch2: define clock ID used for GMAC
  patch3: modify CRU config for Rockchip RK3288 SoCs integrated GMAC
  patch4: dts: rockchip: add gmac info for rk3288
  patch5: dts: rockchip: enable gmac on RK3288 evb board
  patch6: add document for Rockchip RK3288 GMAC

Tested on rk3288 evb board:
Execute the following command to enable ethernet,
set local IP and ping a remote host.

busybox ifconfig eth0 up
busybox ifconfig eth0 192.168.1.111
ping 192.168.1.1
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 9aacfb20 53a83930

Documentation/devicetree/bindings/net/rockchip-dwmac.txt

0 → 100644
+67 −0
Original line number Original line Diff line number Diff line 
Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)



The device node has following properties.



Required properties:

 - compatible: Can be "rockchip,rk3288-gmac".

 - reg: addresses and length of the register sets for the device.

 - interrupts: Should contain the GMAC interrupts.

 - interrupt-names: Should contain the interrupt names "macirq".

 - rockchip,grf: phandle to the syscon grf used to control speed and mode.

 - clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY.

	   <&cru SCLK_MAC_PLL>: PLL clock for SCLK_MAC

	   <&cru SCLK_MAC_RX>: clock gate for RX

	   <&cru SCLK_MAC_TX>: clock gate for TX

	   <&cru SCLK_MACREF>: clock gate for RMII referce clock

	   <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output

	   <&cru ACLK_GMAC>: AXI clock gate for GMAC

	   <&cru PCLK_GMAC>: APB clock gate for GMAC

 - clock-names: One name for each entry in the clocks property.

 - phy-mode: See ethernet.txt file in the same directory.

 - pinctrl-names: Names corresponding to the numbered pinctrl states.

 - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.

 - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)

   is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means

   PHY provides the reference clock(50MHz), "output" means GMAC provides the

   reference clock.

 - snps,reset-gpio       gpio number for phy reset.

 - snps,reset-active-low boolean flag to indicate if phy reset is active low.

 - assigned-clocks: main clock, should be <&cru SCLK_MAC>;

 - assigned-clock-parents = parent of main clock.

   can be <&ext_gmac> or <&cru SCLK_MAC_PLL>.



Optional properties:

 - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.

 - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.



Example:



gmac: ethernet@ff290000 {

	compatible = "rockchip,rk3288-gmac";

	reg = <0xff290000 0x10000>;

	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;

	interrupt-names = "macirq";

	rockchip,grf = <&grf>;

	clocks = <&cru SCLK_MAC>,

		<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,

		<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,

		<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;

	clock-names = "stmmaceth",

		"mac_clk_rx", "mac_clk_tx",

		"clk_mac_ref", "clk_mac_refout",

		"aclk_mac", "pclk_mac";

	phy-mode = "rgmii";

	pinctrl-names = "default";

	pinctrl-0 = <&rgmii_pins /*&rmii_pins*/>;



	clock_in_out = "input";

	snps,reset-gpio = <&gpio4 7 0>;

	snps,reset-active-low;



	assigned-clocks = <&cru SCLK_MAC>;

	assigned-clock-parents = <&ext_gmac>;

	tx_delay = <0x30>;

	rx_delay = <0x10>;



	status = "ok";

};

arch/arm/boot/dts/rk3288-evb-rk808.dts

+23 −0
Original line number Original line Diff line number Diff line
@@ -15,6 +15,13 @@ 




/ {

/ {

	compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";

	compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";



	ext_gmac: external-gmac-clock {

		compatible = "fixed-clock";

		clock-frequency = <125000000>;

		clock-output-names = "ext_gmac";

		#clock-cells = <0>;

	};

};

};





&cpu0 {

&cpu0 {
@@ -152,3 +159,19 @@ 
		};

		};

	};

	};

};

};



&gmac {

	phy_regulator = "vcc_phy";

	phy-mode = "rgmii";

	clock_in_out = "input";

	snps,reset-gpio = <&gpio4 7 0>;

	snps,reset-active-low;

	snps,reset-delays-us = <0 10000 1000000>;

	assigned-clocks = <&cru SCLK_MAC>;

	assigned-clock-parents = <&ext_gmac>;

	pinctrl-names = "default";

	pinctrl-0 = <&rgmii_pins>;

	tx_delay = <0x30>;

	rx_delay = <0x10>;

	status = "ok";

};

arch/arm/boot/dts/rk3288-evb.dtsi

+17 −0
Original line number Original line Diff line number Diff line
@@ -90,6 +90,17 @@ 
		regulator-always-on;

		regulator-always-on;

		regulator-boot-on;

		regulator-boot-on;

	};

	};



	vcc_phy: vcc-phy-regulator {

		compatible = "regulator-fixed";

		enable-active-high;

		gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>;

		pinctrl-names = "default";

		pinctrl-0 = <&eth_phy_pwr>;

		regulator-name = "vcc_phy";

		regulator-always-on;

		regulator-boot-on;

	};

};

};





&emmc {

&emmc {
@@ -178,6 +189,12 @@ 
			rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;

			rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;

		};

		};

	};

	};



	eth_phy {

		eth_phy_pwr: eth-phy-pwr {

			rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>;

		};

	};

};

};





&usb_host0_ehci {

&usb_host0_ehci {

arch/arm/boot/dts/rk3288.dtsi

+54 −0
Original line number Original line Diff line number Diff line
@@ -380,6 +380,22 @@ 
		status = "disabled";

		status = "disabled";

	};

	};





	gmac: ethernet@ff290000 {

		compatible = "rockchip,rk3288-gmac";

		reg = <0xff290000 0x10000>;

		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "macirq";

		rockchip,grf = <&grf>;

		clocks = <&cru SCLK_MAC>,

			<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,

			<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,

			<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;

		clock-names = "stmmaceth",

			"mac_clk_rx", "mac_clk_tx",

			"clk_mac_ref", "clk_mac_refout",

			"aclk_mac", "pclk_mac";

	};



	usb_host0_ehci: usb@ff500000 {

	usb_host0_ehci: usb@ff500000 {

		compatible = "generic-ehci";

		compatible = "generic-ehci";

		reg = <0xff500000 0x100>;

		reg = <0xff500000 0x100>;
@@ -725,6 +741,11 @@ 
			bias-disable;

			bias-disable;

		};

		};





		pcfg_pull_none_12ma: pcfg-pull-none-12ma {

			bias-disable;

			drive-strength = <12>;

		};



		i2c0 {

		i2c0 {

			i2c0_xfer: i2c0-xfer {

			i2c0_xfer: i2c0-xfer {

				rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,

				rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
@@ -1068,5 +1089,38 @@ 
				rockchip,pins = <7 23 3 &pcfg_pull_none>;

				rockchip,pins = <7 23 3 &pcfg_pull_none>;

			};

			};

		};

		};



		gmac {

			rgmii_pins: rgmii-pins {

				rockchip,pins = <3 30 3 &pcfg_pull_none>,

						<3 31 3 &pcfg_pull_none>,

						<3 26 3 &pcfg_pull_none>,

						<3 27 3 &pcfg_pull_none>,

						<3 28 3 &pcfg_pull_none_12ma>,

						<3 29 3 &pcfg_pull_none_12ma>,

						<3 24 3 &pcfg_pull_none_12ma>,

						<3 25 3 &pcfg_pull_none_12ma>,

						<4 0 3 &pcfg_pull_none>,

						<4 5 3 &pcfg_pull_none>,

						<4 6 3 &pcfg_pull_none>,

						<4 9 3 &pcfg_pull_none_12ma>,

						<4 4 3 &pcfg_pull_none_12ma>,

						<4 1 3 &pcfg_pull_none>,

						<4 3 3 &pcfg_pull_none>;

			};



			rmii_pins: rmii-pins {

				rockchip,pins = <3 30 3 &pcfg_pull_none>,

						<3 31 3 &pcfg_pull_none>,

						<3 28 3 &pcfg_pull_none>,

						<3 29 3 &pcfg_pull_none>,

						<4 0 3 &pcfg_pull_none>,

						<4 5 3 &pcfg_pull_none>,

						<4 4 3 &pcfg_pull_none>,

						<4 1 3 &pcfg_pull_none>,

						<4 2 3 &pcfg_pull_none>,

						<4 3 3 &pcfg_pull_none>;

			};

		};

	};

	};

};
 
};

drivers/clk/rockchip/clk-rk3288.c

+7 −7
Original line number Original line Diff line number Diff line
@@ -190,7 +190,7 @@ PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; 
PNAME(mux_uart3_p)	= { "uart3_src", "uart3_frac", "xin24m" };

PNAME(mux_uart3_p)	= { "uart3_src", "uart3_frac", "xin24m" };

PNAME(mux_uart4_p)	= { "uart4_src", "uart4_frac", "xin24m" };

PNAME(mux_uart4_p)	= { "uart4_src", "uart4_frac", "xin24m" };

PNAME(mux_cif_out_p)	= { "cif_src", "xin24m" };

PNAME(mux_cif_out_p)	= { "cif_src", "xin24m" };

PNAME(mux_macref_p)	= { "mac_src", "ext_gmac" };

PNAME(mux_mac_p)	= { "mac_pll_src", "ext_gmac" };

PNAME(mux_hsadcout_p)	= { "hsadc_src", "ext_hsadc" };

PNAME(mux_hsadcout_p)	= { "hsadc_src", "ext_hsadc" };

PNAME(mux_edp_24m_p)	= { "ext_edp_24m", "xin24m" };

PNAME(mux_edp_24m_p)	= { "ext_edp_24m", "xin24m" };

PNAME(mux_tspout_p)	= { "cpll", "gpll", "npll", "xin27m" };

PNAME(mux_tspout_p)	= { "cpll", "gpll", "npll", "xin27m" };
@@ -575,18 +575,18 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { 
	MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, 0,

	MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, 0,

			RK3288_CLKSEL_CON(3), 8, 2, MFLAGS),

			RK3288_CLKSEL_CON(3), 8, 2, MFLAGS),





	COMPOSITE(0, "mac_src", mux_pll_src_npll_cpll_gpll_p, 0,

	COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,

			RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,

			RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,

			RK3288_CLKGATE_CON(2), 5, GFLAGS),

			RK3288_CLKGATE_CON(2), 5, GFLAGS),

	MUX(0, "macref", mux_macref_p, 0,

	MUX(SCLK_MAC, "mac_clk", mux_mac_p, 0,

			RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),

			RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),

	GATE(0, "sclk_macref_out", "macref", 0,

	GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,

			RK3288_CLKGATE_CON(5), 3, GFLAGS),

			RK3288_CLKGATE_CON(5), 3, GFLAGS),

	GATE(SCLK_MACREF, "sclk_macref", "macref", 0,

	GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,

			RK3288_CLKGATE_CON(5), 2, GFLAGS),

			RK3288_CLKGATE_CON(5), 2, GFLAGS),

	GATE(SCLK_MAC_RX, "sclk_mac_rx", "macref", 0,

	GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,

			RK3288_CLKGATE_CON(5), 0, GFLAGS),

			RK3288_CLKGATE_CON(5), 0, GFLAGS),

	GATE(SCLK_MAC_TX, "sclk_mac_tx", "macref", 0,

	GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,

			RK3288_CLKGATE_CON(5), 1, GFLAGS),

			RK3288_CLKGATE_CON(5), 1, GFLAGS),





	COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,

	COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,