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Commit ff877c49 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drivers2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull "ARM: More SoC driver updates" from Olof Johansson:
 "This branch contains a handful of driver updates, mostly to the
  LPC32xx platform but also for Samsung EXYNOS and Davinci.

  It had a few context conflicts against patches already merged through
  fixes-non-critical.  We should have resolved this early during the
  development cycle by pulling them in as a dependency, instead I did it
  after the fact this time."

* tag 'drivers2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  gpio/samsung: use ioremap() for EXYNOS4 GPIOlib
  gpio/samsung: add support GPIOlib for EXYNOS5250
  ARM: EXYNOS: add support GPIO for EXYNOS5250
  ARM: LPC32xx: Ethernet support
  ARM: LPC32xx: USB Support
  ARM: davinci: dm644x evm: add support for VPBE display
  ARM: davinci: dm644x: add support for v4l2 video display
  ARM: EXYNOS: Hook up JPEG PD to generic PD infrastructure
  ARM: EXYNOS: Hook up G2D PD to generic PD infrastructure
  arm: lpc32xx: phy3250: add rtc & touch device
  ARM: LPC32xx: clock.c: Clock registration fixes
  ARM: LPC32xx: clock.c: jiffies wrapping
  ARM: LPC32xx: clock.c: Missing header file
  ARM: LPC32XX: Remove broken non-static declaration
  ARM: LPC32xx: clock.c: Fix mutex lock issues
  ARM: LPC32xx: clock.c: warning fix
  ARM: LPC32xx: Added lpc32xx_defconfig
parents 529b73fc 1f5b7dcf

arch/arm/mach-davinci/board-dm644x-evm.c

+108 −1
Original line number Diff line number Diff line
@@ -613,6 +613,113 @@ static void __init evm_init_i2c(void) 
	i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));

}



#define VENC_STD_ALL	(V4L2_STD_NTSC | V4L2_STD_PAL)



/* venc standard timings */

static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {

	{

		.name		= "ntsc",

		.timings_type	= VPBE_ENC_STD,

		.timings	= {V4L2_STD_525_60},

		.interlaced	= 1,

		.xres		= 720,

		.yres		= 480,

		.aspect		= {11, 10},

		.fps		= {30000, 1001},

		.left_margin	= 0x79,

		.upper_margin	= 0x10,

	},

	{

		.name		= "pal",

		.timings_type	= VPBE_ENC_STD,

		.timings	= {V4L2_STD_625_50},

		.interlaced	= 1,

		.xres		= 720,

		.yres		= 576,

		.aspect		= {54, 59},

		.fps		= {25, 1},

		.left_margin	= 0x7e,

		.upper_margin	= 0x16,

	},

};



/* venc dv preset timings */

static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {

	{

		.name		= "480p59_94",

		.timings_type	= VPBE_ENC_DV_PRESET,

		.timings	= {V4L2_DV_480P59_94},

		.interlaced	= 0,

		.xres		= 720,

		.yres		= 480,

		.aspect		= {1, 1},

		.fps		= {5994, 100},

		.left_margin	= 0x80,

		.upper_margin	= 0x20,

	},

	{

		.name		= "576p50",

		.timings_type	= VPBE_ENC_DV_PRESET,

		.timings	= {V4L2_DV_576P50},

		.interlaced	= 0,

		.xres		= 720,

		.yres		= 576,

		.aspect		= {1, 1},

		.fps		= {50, 1},

		.left_margin	= 0x7e,

		.upper_margin	= 0x30,

	},

};



/*

 * The outputs available from VPBE + encoders. Keep the order same

 * as that of encoders. First those from venc followed by that from

 * encoders. Index in the output refers to index on a particular encoder.

 * Driver uses this index to pass it to encoder when it supports more

 * than one output. Userspace applications use index of the array to

 * set an output.

 */

static struct vpbe_output dm644xevm_vpbe_outputs[] = {

	{

		.output		= {

			.index		= 0,

			.name		= "Composite",

			.type		= V4L2_OUTPUT_TYPE_ANALOG,

			.std		= VENC_STD_ALL,

			.capabilities	= V4L2_OUT_CAP_STD,

		},

		.subdev_name	= VPBE_VENC_SUBDEV_NAME,

		.default_mode	= "ntsc",

		.num_modes	= ARRAY_SIZE(dm644xevm_enc_std_timing),

		.modes		= dm644xevm_enc_std_timing,

	},

	{

		.output		= {

			.index		= 1,

			.name		= "Component",

			.type		= V4L2_OUTPUT_TYPE_ANALOG,

			.capabilities	= V4L2_OUT_CAP_PRESETS,

		},

		.subdev_name	= VPBE_VENC_SUBDEV_NAME,

		.default_mode	= "480p59_94",

		.num_modes	= ARRAY_SIZE(dm644xevm_enc_preset_timing),

		.modes		= dm644xevm_enc_preset_timing,

	},

};



static struct vpbe_config dm644xevm_display_cfg = {

	.module_name	= "dm644x-vpbe-display",

	.i2c_adapter_id	= 1,

	.osd		= {

		.module_name	= VPBE_OSD_SUBDEV_NAME,

	},

	.venc		= {

		.module_name	= VPBE_VENC_SUBDEV_NAME,

	},

	.num_outputs	= ARRAY_SIZE(dm644xevm_vpbe_outputs),

	.outputs	= dm644xevm_vpbe_outputs,

};



static struct platform_device *davinci_evm_devices[] __initdata = {

	&davinci_fb_device,

	&rtc_dev,
@@ -696,7 +803,7 @@ static __init void davinci_evm_init(void) 
	evm_init_i2c();



	davinci_setup_mmc(0, &dm6446evm_mmc_config);

	dm644x_init_video(&dm644xevm_capture_cfg);

	dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg);



	davinci_serial_init(&uart_config);

	dm644x_init_asp(&dm644x_evm_snd_data);

arch/arm/mach-davinci/davinci.h

+7 −1
Original line number Diff line number Diff line
@@ -29,9 +29,15 @@ 


#include <media/davinci/vpfe_capture.h>

#include <media/davinci/vpif_types.h>

#include <media/davinci/vpss.h>

#include <media/davinci/vpbe_types.h>

#include <media/davinci/vpbe_venc.h>

#include <media/davinci/vpbe.h>

#include <media/davinci/vpbe_osd.h>



#define DAVINCI_SYSTEM_MODULE_BASE	0x01c40000

#define SYSMOD_VIDCLKCTL		0x38

#define SYSMOD_VPSS_CLKCTL		0x44

#define SYSMOD_VDD3P3VPWDN		0x48

#define SYSMOD_VSCLKDIS			0x6c

#define SYSMOD_PUPDCTL1			0x7c
@@ -83,7 +89,7 @@ void dm365_set_vpfe_config(struct vpfe_config *cfg); 
/* DM644x function declarations */

void __init dm644x_init(void);

void __init dm644x_init_asp(struct snd_platform_data *pdata);

int __init dm644x_init_video(struct vpfe_config *);

int __init dm644x_init_video(struct vpfe_config *, struct vpbe_config *);



/* DM646x function declarations */

void __init dm646x_init(void);

arch/arm/mach-davinci/dm644x.c

+153 −13
Original line number Diff line number Diff line
@@ -627,7 +627,7 @@ static struct resource dm644x_vpfe_resources[] = { 
	},

};



static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);

static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);

static struct resource dm644x_ccdc_resource[] = {

	/* CCDC Base address */

	{
@@ -643,7 +643,7 @@ static struct platform_device dm644x_ccdc_dev = { 
	.num_resources  = ARRAY_SIZE(dm644x_ccdc_resource),

	.resource       = dm644x_ccdc_resource,

	.dev = {

		.dma_mask               = &vpfe_capture_dma_mask,

		.dma_mask               = &dm644x_video_dma_mask,

		.coherent_dma_mask      = DMA_BIT_MASK(32),

	},

};
@@ -654,7 +654,134 @@ static struct platform_device dm644x_vpfe_dev = { 
	.num_resources	= ARRAY_SIZE(dm644x_vpfe_resources),

	.resource	= dm644x_vpfe_resources,

	.dev = {

		.dma_mask		= &vpfe_capture_dma_mask,

		.dma_mask		= &dm644x_video_dma_mask,

		.coherent_dma_mask	= DMA_BIT_MASK(32),

	},

};



#define DM644X_OSD_BASE		0x01c72600



static struct resource dm644x_osd_resources[] = {

	{

		.start	= DM644X_OSD_BASE,

		.end	= DM644X_OSD_BASE + 0x1ff,

		.flags	= IORESOURCE_MEM,

	},

};



static struct osd_platform_data dm644x_osd_data = {

	.vpbe_type     = VPBE_VERSION_1,

};



static struct platform_device dm644x_osd_dev = {

	.name		= VPBE_OSD_SUBDEV_NAME,

	.id		= -1,

	.num_resources	= ARRAY_SIZE(dm644x_osd_resources),

	.resource	= dm644x_osd_resources,

	.dev		= {

		.dma_mask		= &dm644x_video_dma_mask,

		.coherent_dma_mask	= DMA_BIT_MASK(32),

		.platform_data		= &dm644x_osd_data,

	},

};



#define DM644X_VENC_BASE		0x01c72400



static struct resource dm644x_venc_resources[] = {

	{

		.start	= DM644X_VENC_BASE,

		.end	= DM644X_VENC_BASE + 0x17f,

		.flags	= IORESOURCE_MEM,

	},

};



#define DM644X_VPSS_MUXSEL_PLL2_MODE          BIT(0)

#define DM644X_VPSS_MUXSEL_VPBECLK_MODE       BIT(1)

#define DM644X_VPSS_VENCLKEN                  BIT(3)

#define DM644X_VPSS_DACCLKEN                  BIT(4)



static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,

				   unsigned int mode)

{

	int ret = 0;

	u32 v = DM644X_VPSS_VENCLKEN;



	switch (type) {

	case VPBE_ENC_STD:

		v |= DM644X_VPSS_DACCLKEN;

		writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));

		break;

	case VPBE_ENC_DV_PRESET:

		switch (mode) {

		case V4L2_DV_480P59_94:

		case V4L2_DV_576P50:

			v |= DM644X_VPSS_MUXSEL_PLL2_MODE |

			     DM644X_VPSS_DACCLKEN;

			writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));

			break;

		case V4L2_DV_720P60:

		case V4L2_DV_1080I60:

		case V4L2_DV_1080P30:

			/*

			 * For HD, use external clock source since

			 * HD requires higher clock rate

			 */

			v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;

			writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));

			break;

		default:

			ret = -EINVAL;

			break;

		}

		break;

	default:

		ret  = -EINVAL;

	}



	return ret;

}



static struct resource dm644x_v4l2_disp_resources[] = {

	{

		.start	= IRQ_VENCINT,

		.end	= IRQ_VENCINT,

		.flags	= IORESOURCE_IRQ,

	},

};



static struct platform_device dm644x_vpbe_display = {

	.name		= "vpbe-v4l2",

	.id		= -1,

	.num_resources	= ARRAY_SIZE(dm644x_v4l2_disp_resources),

	.resource	= dm644x_v4l2_disp_resources,

	.dev		= {

		.dma_mask		= &dm644x_video_dma_mask,

		.coherent_dma_mask	= DMA_BIT_MASK(32),

	},

};



static struct venc_platform_data dm644x_venc_pdata = {

	.venc_type	= VPBE_VERSION_1,

	.setup_clock	= dm644x_venc_setup_clock,

};



static struct platform_device dm644x_venc_dev = {

	.name		= VPBE_VENC_SUBDEV_NAME,

	.id		= -1,

	.num_resources	= ARRAY_SIZE(dm644x_venc_resources),

	.resource	= dm644x_venc_resources,

	.dev		= {

		.dma_mask		= &dm644x_video_dma_mask,

		.coherent_dma_mask	= DMA_BIT_MASK(32),

		.platform_data		= &dm644x_venc_pdata,

	},

};



static struct platform_device dm644x_vpbe_dev = {

	.name		= "vpbe_controller",

	.id		= -1,

	.dev		= {

		.dma_mask		= &dm644x_video_dma_mask,

		.coherent_dma_mask	= DMA_BIT_MASK(32),

	},

};
@@ -786,17 +913,30 @@ void __init dm644x_init(void) 
	davinci_map_sysmod();

}



int __init dm644x_init_video(struct vpfe_config *vpfe_cfg)

int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,

				struct vpbe_config *vpbe_cfg)

{

	dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;



	/* Add ccdc clock aliases */

	clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL);

	clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL);



	if (vpfe_cfg || vpbe_cfg)

		platform_device_register(&dm644x_vpss_device);



	if (vpfe_cfg) {

		dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;

		platform_device_register(&dm644x_ccdc_dev);

		platform_device_register(&dm644x_vpfe_dev);

		/* Add ccdc clock aliases */

		clk_add_alias("master", dm644x_ccdc_dev.name,

			      "vpss_master", NULL);

		clk_add_alias("slave", dm644x_ccdc_dev.name,

			      "vpss_slave", NULL);

	}



	if (vpbe_cfg) {

		dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;

		platform_device_register(&dm644x_osd_dev);

		platform_device_register(&dm644x_venc_dev);

		platform_device_register(&dm644x_vpbe_dev);

		platform_device_register(&dm644x_vpbe_display);

	}



	return 0;

}

arch/arm/mach-exynos/common.c

+0 −15
Original line number Diff line number Diff line
@@ -159,21 +159,6 @@ static struct map_desc exynos4_iodesc[] __initdata = { 
		.pfn		= __phys_to_pfn(EXYNOS4_PA_L2CC),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_GPIO1,

		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO1),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_GPIO2,

		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO2),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_GPIO3,

		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO3),

		.length		= SZ_256,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_DMC0,

		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC0),

arch/arm/mach-exynos/include/mach/gpio.h

+188 −51
Original line number Diff line number Diff line 
/* linux/arch/arm/mach-exynos4/include/mach/gpio.h

 *

 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.

/*

 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *

 * EXYNOS4 - GPIO lib support

 * EXYNOS - GPIO lib support

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as
@@ -13,9 +12,13 @@ 
#ifndef __ASM_ARCH_GPIO_H

#define __ASM_ARCH_GPIO_H __FILE__



/* Practically, GPIO banks up to GPZ are the configurable gpio banks */

/* Macro for EXYNOS GPIO numbering */



#define EXYNOS_GPIO_NEXT(__gpio) \

	((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)



/* EXYNOS4 GPIO bank sizes */



/* GPIO bank sizes */

#define EXYNOS4_GPIO_A0_NR	(8)

#define EXYNOS4_GPIO_A1_NR	(6)

#define EXYNOS4_GPIO_B_NR	(8)
@@ -54,52 +57,50 @@ 
#define EXYNOS4_GPIO_Y6_NR	(8)

#define EXYNOS4_GPIO_Z_NR	(7)



/* GPIO bank numbers */



#define EXYNOS4_GPIO_NEXT(__gpio) \

	((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)

/* EXYNOS4 GPIO bank numbers */



enum s5p_gpio_number {

enum exynos4_gpio_number {

	EXYNOS4_GPIO_A0_START	= 0,

	EXYNOS4_GPIO_A1_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0),

	EXYNOS4_GPIO_B_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1),

	EXYNOS4_GPIO_C0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B),

	EXYNOS4_GPIO_C1_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0),

	EXYNOS4_GPIO_D0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1),

	EXYNOS4_GPIO_D1_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0),

	EXYNOS4_GPIO_E0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1),

	EXYNOS4_GPIO_E1_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E0),

	EXYNOS4_GPIO_E2_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E1),

	EXYNOS4_GPIO_E3_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E2),

	EXYNOS4_GPIO_E4_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E3),

	EXYNOS4_GPIO_F0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E4),

	EXYNOS4_GPIO_F1_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0),

	EXYNOS4_GPIO_F2_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1),

	EXYNOS4_GPIO_F3_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2),

	EXYNOS4_GPIO_J0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3),

	EXYNOS4_GPIO_J1_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J0),

	EXYNOS4_GPIO_K0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J1),

	EXYNOS4_GPIO_K1_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0),

	EXYNOS4_GPIO_K2_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1),

	EXYNOS4_GPIO_K3_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2),

	EXYNOS4_GPIO_L0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3),

	EXYNOS4_GPIO_L1_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0),

	EXYNOS4_GPIO_L2_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1),

	EXYNOS4_GPIO_X0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2),

	EXYNOS4_GPIO_X1_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0),

	EXYNOS4_GPIO_X2_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1),

	EXYNOS4_GPIO_X3_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2),

	EXYNOS4_GPIO_Y0_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3),

	EXYNOS4_GPIO_Y1_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y0),

	EXYNOS4_GPIO_Y2_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y1),

	EXYNOS4_GPIO_Y3_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y2),

	EXYNOS4_GPIO_Y4_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y3),

	EXYNOS4_GPIO_Y5_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y4),

	EXYNOS4_GPIO_Y6_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y5),

	EXYNOS4_GPIO_Z_START	= EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y6),

	EXYNOS4_GPIO_A1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A0),

	EXYNOS4_GPIO_B_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A1),

	EXYNOS4_GPIO_C0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_B),

	EXYNOS4_GPIO_C1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),

	EXYNOS4_GPIO_D0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),

	EXYNOS4_GPIO_D1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),

	EXYNOS4_GPIO_E0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),

	EXYNOS4_GPIO_E1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),

	EXYNOS4_GPIO_E2_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),

	EXYNOS4_GPIO_E3_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),

	EXYNOS4_GPIO_E4_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),

	EXYNOS4_GPIO_F0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),

	EXYNOS4_GPIO_F1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),

	EXYNOS4_GPIO_F2_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),

	EXYNOS4_GPIO_F3_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),

	EXYNOS4_GPIO_J0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F3),

	EXYNOS4_GPIO_J1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J0),

	EXYNOS4_GPIO_K0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J1),

	EXYNOS4_GPIO_K1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K0),

	EXYNOS4_GPIO_K2_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K1),

	EXYNOS4_GPIO_K3_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K2),

	EXYNOS4_GPIO_L0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K3),

	EXYNOS4_GPIO_L1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L0),

	EXYNOS4_GPIO_L2_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L1),

	EXYNOS4_GPIO_X0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L2),

	EXYNOS4_GPIO_X1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X0),

	EXYNOS4_GPIO_X2_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X1),

	EXYNOS4_GPIO_X3_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X2),

	EXYNOS4_GPIO_Y0_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X3),

	EXYNOS4_GPIO_Y1_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y0),

	EXYNOS4_GPIO_Y2_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y1),

	EXYNOS4_GPIO_Y3_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y2),

	EXYNOS4_GPIO_Y4_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y3),

	EXYNOS4_GPIO_Y5_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y4),

	EXYNOS4_GPIO_Y6_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y5),

	EXYNOS4_GPIO_Z_START	= EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6),

};



/* EXYNOS4 GPIO number definitions */



#define EXYNOS4_GPA0(_nr)	(EXYNOS4_GPIO_A0_START + (_nr))

#define EXYNOS4_GPA1(_nr)	(EXYNOS4_GPIO_A1_START + (_nr))

#define EXYNOS4_GPB(_nr)	(EXYNOS4_GPIO_B_START + (_nr))
@@ -139,11 +140,147 @@ enum s5p_gpio_number { 
#define EXYNOS4_GPZ(_nr)	(EXYNOS4_GPIO_Z_START + (_nr))



/* the end of the EXYNOS4 specific gpios */



#define EXYNOS4_GPIO_END	(EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)

#define S3C_GPIO_END		EXYNOS4_GPIO_END



/* define the number of gpios we need to the one after the GPZ() range */

#define ARCH_NR_GPIOS		(EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) +	\

				 CONFIG_SAMSUNG_GPIO_EXTRA + 1)

/* EXYNOS5 GPIO bank sizes */



#define EXYNOS5_GPIO_A0_NR	(8)

#define EXYNOS5_GPIO_A1_NR	(6)

#define EXYNOS5_GPIO_A2_NR	(8)

#define EXYNOS5_GPIO_B0_NR	(5)

#define EXYNOS5_GPIO_B1_NR	(5)

#define EXYNOS5_GPIO_B2_NR	(4)

#define EXYNOS5_GPIO_B3_NR	(4)

#define EXYNOS5_GPIO_C0_NR	(7)

#define EXYNOS5_GPIO_C1_NR	(7)

#define EXYNOS5_GPIO_C2_NR	(7)

#define EXYNOS5_GPIO_C3_NR	(7)

#define EXYNOS5_GPIO_D0_NR	(8)

#define EXYNOS5_GPIO_D1_NR	(8)

#define EXYNOS5_GPIO_Y0_NR	(6)

#define EXYNOS5_GPIO_Y1_NR	(4)

#define EXYNOS5_GPIO_Y2_NR	(6)

#define EXYNOS5_GPIO_Y3_NR	(8)

#define EXYNOS5_GPIO_Y4_NR	(8)

#define EXYNOS5_GPIO_Y5_NR	(8)

#define EXYNOS5_GPIO_Y6_NR	(8)

#define EXYNOS5_GPIO_X0_NR	(8)

#define EXYNOS5_GPIO_X1_NR	(8)

#define EXYNOS5_GPIO_X2_NR	(8)

#define EXYNOS5_GPIO_X3_NR	(8)

#define EXYNOS5_GPIO_E0_NR	(8)

#define EXYNOS5_GPIO_E1_NR	(2)

#define EXYNOS5_GPIO_F0_NR	(4)

#define EXYNOS5_GPIO_F1_NR	(4)

#define EXYNOS5_GPIO_G0_NR	(8)

#define EXYNOS5_GPIO_G1_NR	(8)

#define EXYNOS5_GPIO_G2_NR	(2)

#define EXYNOS5_GPIO_H0_NR	(4)

#define EXYNOS5_GPIO_H1_NR	(8)

#define EXYNOS5_GPIO_V0_NR	(8)

#define EXYNOS5_GPIO_V1_NR	(8)

#define EXYNOS5_GPIO_V2_NR	(8)

#define EXYNOS5_GPIO_V3_NR	(8)

#define EXYNOS5_GPIO_V4_NR	(2)

#define EXYNOS5_GPIO_Z_NR	(7)



/* EXYNOS5 GPIO bank numbers */



enum exynos5_gpio_number {

	EXYNOS5_GPIO_A0_START		= 0,

	EXYNOS5_GPIO_A1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A0),

	EXYNOS5_GPIO_A2_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A1),

	EXYNOS5_GPIO_B0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A2),

	EXYNOS5_GPIO_B1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B0),

	EXYNOS5_GPIO_B2_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B1),

	EXYNOS5_GPIO_B3_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B2),

	EXYNOS5_GPIO_C0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B3),

	EXYNOS5_GPIO_C1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),

	EXYNOS5_GPIO_C2_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),

	EXYNOS5_GPIO_C3_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),

	EXYNOS5_GPIO_D0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),

	EXYNOS5_GPIO_D1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),

	EXYNOS5_GPIO_Y0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),

	EXYNOS5_GPIO_Y1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),

	EXYNOS5_GPIO_Y2_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y1),

	EXYNOS5_GPIO_Y3_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y2),

	EXYNOS5_GPIO_Y4_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y3),

	EXYNOS5_GPIO_Y5_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y4),

	EXYNOS5_GPIO_Y6_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y5),

	EXYNOS5_GPIO_X0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y6),

	EXYNOS5_GPIO_X1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X0),

	EXYNOS5_GPIO_X2_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X1),

	EXYNOS5_GPIO_X3_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X2),

	EXYNOS5_GPIO_E0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X3),

	EXYNOS5_GPIO_E1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E0),

	EXYNOS5_GPIO_F0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E1),

	EXYNOS5_GPIO_F1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F0),

	EXYNOS5_GPIO_G0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F1),

	EXYNOS5_GPIO_G1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G0),

	EXYNOS5_GPIO_G2_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G1),

	EXYNOS5_GPIO_H0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G2),

	EXYNOS5_GPIO_H1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H0),

	EXYNOS5_GPIO_V0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H1),

	EXYNOS5_GPIO_V1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V0),

	EXYNOS5_GPIO_V2_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V1),

	EXYNOS5_GPIO_V3_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V2),

	EXYNOS5_GPIO_V4_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V3),

	EXYNOS5_GPIO_Z_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V4),

};



/* EXYNOS5 GPIO number definitions */



#define EXYNOS5_GPA0(_nr)	(EXYNOS5_GPIO_A0_START + (_nr))

#define EXYNOS5_GPA1(_nr)	(EXYNOS5_GPIO_A1_START + (_nr))

#define EXYNOS5_GPA2(_nr)	(EXYNOS5_GPIO_A2_START + (_nr))

#define EXYNOS5_GPB0(_nr)	(EXYNOS5_GPIO_B0_START + (_nr))

#define EXYNOS5_GPB1(_nr)	(EXYNOS5_GPIO_B1_START + (_nr))

#define EXYNOS5_GPB2(_nr)	(EXYNOS5_GPIO_B2_START + (_nr))

#define EXYNOS5_GPB3(_nr)	(EXYNOS5_GPIO_B3_START + (_nr))

#define EXYNOS5_GPC0(_nr)	(EXYNOS5_GPIO_C0_START + (_nr))

#define EXYNOS5_GPC1(_nr)	(EXYNOS5_GPIO_C1_START + (_nr))

#define EXYNOS5_GPC2(_nr)	(EXYNOS5_GPIO_C2_START + (_nr))

#define EXYNOS5_GPC3(_nr)	(EXYNOS5_GPIO_C3_START + (_nr))

#define EXYNOS5_GPD0(_nr)	(EXYNOS5_GPIO_D0_START + (_nr))

#define EXYNOS5_GPD1(_nr)	(EXYNOS5_GPIO_D1_START + (_nr))

#define EXYNOS5_GPY0(_nr)	(EXYNOS5_GPIO_Y0_START + (_nr))

#define EXYNOS5_GPY1(_nr)	(EXYNOS5_GPIO_Y1_START + (_nr))

#define EXYNOS5_GPY2(_nr)	(EXYNOS5_GPIO_Y2_START + (_nr))

#define EXYNOS5_GPY3(_nr)	(EXYNOS5_GPIO_Y3_START + (_nr))

#define EXYNOS5_GPY4(_nr)	(EXYNOS5_GPIO_Y4_START + (_nr))

#define EXYNOS5_GPY5(_nr)	(EXYNOS5_GPIO_Y5_START + (_nr))

#define EXYNOS5_GPY6(_nr)	(EXYNOS5_GPIO_Y6_START + (_nr))

#define EXYNOS5_GPX0(_nr)	(EXYNOS5_GPIO_X0_START + (_nr))

#define EXYNOS5_GPX1(_nr)	(EXYNOS5_GPIO_X1_START + (_nr))

#define EXYNOS5_GPX2(_nr)	(EXYNOS5_GPIO_X2_START + (_nr))

#define EXYNOS5_GPX3(_nr)	(EXYNOS5_GPIO_X3_START + (_nr))

#define EXYNOS5_GPE0(_nr)	(EXYNOS5_GPIO_E0_START + (_nr))

#define EXYNOS5_GPE1(_nr)	(EXYNOS5_GPIO_E1_START + (_nr))

#define EXYNOS5_GPF0(_nr)	(EXYNOS5_GPIO_F0_START + (_nr))

#define EXYNOS5_GPF1(_nr)	(EXYNOS5_GPIO_F1_START + (_nr))

#define EXYNOS5_GPG0(_nr)	(EXYNOS5_GPIO_G0_START + (_nr))

#define EXYNOS5_GPG1(_nr)	(EXYNOS5_GPIO_G1_START + (_nr))

#define EXYNOS5_GPG2(_nr)	(EXYNOS5_GPIO_G2_START + (_nr))

#define EXYNOS5_GPH0(_nr)	(EXYNOS5_GPIO_H0_START + (_nr))

#define EXYNOS5_GPH1(_nr)	(EXYNOS5_GPIO_H1_START + (_nr))

#define EXYNOS5_GPV0(_nr)	(EXYNOS5_GPIO_V0_START + (_nr))

#define EXYNOS5_GPV1(_nr)	(EXYNOS5_GPIO_V1_START + (_nr))

#define EXYNOS5_GPV2(_nr)	(EXYNOS5_GPIO_V2_START + (_nr))

#define EXYNOS5_GPV3(_nr)	(EXYNOS5_GPIO_V3_START + (_nr))

#define EXYNOS5_GPV4(_nr)	(EXYNOS5_GPIO_V4_START + (_nr))

#define EXYNOS5_GPZ(_nr)	(EXYNOS5_GPIO_Z_START + (_nr))



/* the end of the EXYNOS5 specific gpios */



#define EXYNOS5_GPIO_END	(EXYNOS5_GPZ(EXYNOS5_GPIO_Z_NR) + 1)



/* actually, EXYNOS5_GPIO_END is bigger than EXYNOS4 */



#define S3C_GPIO_END		(EXYNOS5_GPIO_END)



/* define the number of gpios */



#define ARCH_NR_GPIOS		(CONFIG_SAMSUNG_GPIO_EXTRA + S3C_GPIO_END)



#endif /* __ASM_ARCH_GPIO_H */