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Commit fcc14ac1 authored by Jean Delvare's avatar Jean Delvare Committed by Jean Delvare
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hwmon: (coretemp) Improve support of recent Atom CPU models 



Document the new Atom series (Tunnel Creek and Medfield) as being
supported, and list TjMax for the Atom E600 series.

Also enable the Atom tjmax heuristic for these Atom CPU models.

Signed-off-by: default avatarJean Delvare <khali@linux-fr.org>
Reviewed-by: default avatarGuenter Roeck <guenter.roeck@ericsson.com>
Cc: Alexander Stein <alexander.stein@systec-electronic.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: "R, Durgadoss" <durgadoss.r@intel.com>
parent fb09185a

Documentation/hwmon/coretemp

+7 −1
Original line number Diff line number Diff line
@@ -6,7 +6,8 @@ Supported chips: 
    Prefix: 'coretemp'

    CPUID: family 0x6, models 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),

                              0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),

                              0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield)

                              0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield),

                              0x26 (Tunnel Creek Atom), 0x27 (Medfield Atom)

    Datasheet: Intel 64 and IA-32 Architectures Software Developer's Manual

               Volume 3A: System Programming Guide

               http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
@@ -65,6 +66,9 @@ Process Processor TjMax(C) 
		U3400						105

		P4505/P4500 					90



32nm		Atom Processors

		Z2460						90



45nm		Xeon Processors 5400 Quad-Core

		X5492, X5482, X5472, X5470, X5460, X5450	85

		E5472, E5462, E5450/40/30/20/10/05		85
@@ -85,6 +89,8 @@ Process Processor TjMax(C) 
		N475/470/455/450				100

		N280/270					90

		330/230						125

		E680/660/640/620				90

		E680T/660T/640T/620T				110



45nm		Core2 Processors

		Solo ULV SU3500/3300				100

drivers/hwmon/coretemp.c

+2 −1
Original line number Diff line number Diff line
@@ -210,7 +210,8 @@ static int __cpuinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, 


	/* Atom CPUs */



	if (c->x86_model == 0x1c) {

	if (c->x86_model == 0x1c || c->x86_model == 0x26

	    || c->x86_model == 0x27) {

		usemsr_ee = 0;



		host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));