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Commit f615136c authored by Max Filippov's avatar Max Filippov Committed by Chris Zankel
Browse files

xtensa: add SMP support 



This is largely based on SMP code from the xtensa-2.6.29-smp tree by
Piet Delaney, Marc Gauthier, Joe Taylor, Christian Zankel (and possibly
other Tensilica folks).

Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
Signed-off-by: default avatarChris Zankel <chris@zankel.net>
parent 26a8e96a

arch/xtensa/Kconfig

+36 −1
Original line number Diff line number Diff line
@@ -9,7 +9,6 @@ config XTENSA 
	select GENERIC_CLOCKEVENTS

	select VIRT_TO_BUS

	select GENERIC_IRQ_SHOW

	select GENERIC_CPU_DEVICES

	select GENERIC_SCHED_CLOCK

	select MODULES_USE_ELF_RELA

	select GENERIC_PCI_IOMAP
@@ -65,6 +64,9 @@ config MMU 
config VARIANT_IRQ_SWITCH

	def_bool n



config MAY_HAVE_SMP

	def_bool n



menu "Processor type and features"



choice
@@ -105,6 +107,39 @@ config XTENSA_UNALIGNED_USER 


source "kernel/Kconfig.preempt"



config HAVE_SMP

	bool "System Supports SMP (MX)"

	depends on MAY_HAVE_SMP

	select XTENSA_MX

	help

	  This option is use to indicate that the system-on-a-chip (SOC)

	  supports Multiprocessing. Multiprocessor support implemented above

	  the CPU core definition and currently needs to be selected manually.



	  Multiprocessor support in implemented with external cache and

	  interrupt controlers.



	  The MX interrupt distributer adds Interprocessor Interrupts

	  and causes the IRQ numbers to be increased by 4 for devices

	  like the open cores ethernet driver and the serial interface.



	  You still have to select "Enable SMP" to enable SMP on this SOC.



config SMP

	bool "Enable Symmetric multi-processing support"

	depends on HAVE_SMP

	select USE_GENERIC_SMP_HELPERS

	select GENERIC_SMP_IDLE_THREAD

	help

	  Enabled SMP Software; allows more than one CPU/CORE

	  to be activated during startup.



config NR_CPUS

	depends on SMP

	int "Maximum number of CPUs (2-32)"

	range 2 32

	default "4"



config MATH_EMULATION

	bool "Math emulation"

	help

arch/xtensa/include/asm/barrier.h

+3 −1
Original line number Diff line number Diff line
@@ -17,7 +17,9 @@ 
#define wmb() mb()



#ifdef CONFIG_SMP

#error smp_* not defined

#define smp_mb()	mb()

#define smp_rmb()	rmb()

#define smp_wmb()	wmb()

#else

#define smp_mb()	barrier()

#define smp_rmb()	barrier()

arch/xtensa/include/asm/bitops.h

+2 −6
Original line number Diff line number Diff line
@@ -22,12 +22,8 @@ 
#include <asm/processor.h>

#include <asm/byteorder.h>



#ifdef CONFIG_SMP

# error SMP not supported on this architecture

#endif



#define smp_mb__before_clear_bit()	barrier()

#define smp_mb__after_clear_bit()	barrier()

#define smp_mb__before_clear_bit()	smp_mb()

#define smp_mb__after_clear_bit()	smp_mb()



#include <asm-generic/bitops/non-atomic.h>

arch/xtensa/include/asm/cacheflush.h

+25 −15
Original line number Diff line number Diff line 
/*

 * include/asm-xtensa/cacheflush.h

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * (C) 2001 - 2007 Tensilica Inc.

 * (C) 2001 - 2013 Tensilica Inc.

 */



#ifndef _XTENSA_CACHEFLUSH_H

#define _XTENSA_CACHEFLUSH_H



#ifdef __KERNEL__



#include <linux/mm.h>

#include <asm/processor.h>

#include <asm/page.h>
@@ -51,7 +47,6 @@ extern void __invalidate_icache_page(unsigned long); 
extern void __invalidate_icache_range(unsigned long, unsigned long);

extern void __invalidate_dcache_range(unsigned long, unsigned long);





#if XCHAL_DCACHE_IS_WRITEBACK

extern void __flush_invalidate_dcache_all(void);

extern void __flush_dcache_page(unsigned long);
@@ -87,9 +82,22 @@ static inline void __invalidate_icache_page_alias(unsigned long virt, 
 * (see also Documentation/cachetlb.txt)

 */



#if (DCACHE_WAY_SIZE > PAGE_SIZE)

#if (DCACHE_WAY_SIZE > PAGE_SIZE) || defined(CONFIG_SMP)



#ifdef CONFIG_SMP

void flush_cache_all(void);

void flush_cache_range(struct vm_area_struct*, ulong, ulong);

void flush_icache_range(unsigned long start, unsigned long end);

void flush_cache_page(struct vm_area_struct*,

			     unsigned long, unsigned long);

#else

#define flush_cache_all local_flush_cache_all

#define flush_cache_range local_flush_cache_range

#define flush_icache_range local_flush_icache_range

#define flush_cache_page  local_flush_cache_page

#endif



#define flush_cache_all()						\

#define local_flush_cache_all()						\

	do {								\

		__flush_invalidate_dcache_all();			\

		__invalidate_icache_all();				\
@@ -103,9 +111,11 @@ static inline void __invalidate_icache_page_alias(unsigned long virt, 


#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1

extern void flush_dcache_page(struct page*);

extern void flush_cache_range(struct vm_area_struct*, ulong, ulong);

extern void flush_cache_page(struct vm_area_struct*,

			     unsigned long, unsigned long);



void local_flush_cache_range(struct vm_area_struct *vma,

		unsigned long start, unsigned long end);

void local_flush_cache_page(struct vm_area_struct *vma,

		unsigned long address, unsigned long pfn);



#else
@@ -119,13 +129,14 @@ extern void flush_cache_page(struct vm_area_struct*, 
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0

#define flush_dcache_page(page)				do { } while (0)



#define flush_icache_range local_flush_icache_range

#define flush_cache_page(vma, addr, pfn)		do { } while (0)

#define flush_cache_range(vma, start, end)		do { } while (0)



#endif



/* Ensure consistency between data and instruction cache. */

#define flush_icache_range(start,end) 					\

#define local_flush_icache_range(start, end)				\

	do {								\

		__flush_dcache_range(start, (end) - (start));		\

		__invalidate_icache_range(start,(end) - (start));	\
@@ -253,5 +264,4 @@ static inline void flush_invalidate_dcache_unaligned(u32 addr, u32 size) 
	}

}



#endif /* __KERNEL__ */

#endif /* _XTENSA_CACHEFLUSH_H */

arch/xtensa/include/asm/mmu.h

+5 −5
Original line number Diff line number Diff line 
/*

 * include/asm-xtensa/mmu.h

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2001 - 2005 Tensilica Inc.

 * Copyright (C) 2001 - 2013 Tensilica Inc.

 */



#ifndef _XTENSA_MMU_H
@@ -15,8 +13,10 @@ 
#include <asm-generic/mmu.h>

#else



/* Default "unsigned long" context */

typedef unsigned long mm_context_t;

typedef struct {

	unsigned long asid[NR_CPUS];

	unsigned int cpu;

} mm_context_t;



#endif /* CONFIG_MMU */

#endif	/* _XTENSA_MMU_H */