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Commit e419990b authored by Seungwon Jeon's avatar Seungwon Jeon Committed by Chris Ball
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mmc: dw_mmc: correct the calculation for CLKDIV 



In case of "host->bus_hz < slot->clock", divider value is
miscalculated. And clock divider register value is multiple of 2. If
calculated divider value is odd number, result can be over-clocking.

Signed-off-by: default avatarSeungwon Jeon <tgih.jun@samsung.com>
Acked-by: default avatarWill Newton <will.newton@gmail.com>
Signed-off-by: default avatarChris Ball <cjb@laptop.org>
parent fda5f736

drivers/mmc/host/dw_mmc.c

+5 −4
Original line number Diff line number Diff line
@@ -617,14 +617,15 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot) 
	u32 div;



	if (slot->clock != host->current_speed) {

		if (host->bus_hz % slot->clock)

		div = host->bus_hz / slot->clock;

		if (host->bus_hz % slot->clock && host->bus_hz > slot->clock)

			/*

			 * move the + 1 after the divide to prevent

			 * over-clocking the card.

			 */

			div = ((host->bus_hz / slot->clock) >> 1) + 1;

		else

			div = (host->bus_hz  / slot->clock) >> 1;

			div += 1;



		div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0;



		dev_info(&slot->mmc->class_dev,

			 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"