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Commit e3ea94a6 authored by Marek Olšák's avatar Marek Olšák Committed by Alex Deucher
Browse files

drm/radeon: set correct number of banks for CIK chips in DCE 



We don't have the NUM_BANKS parameter, so we have to calculate it
from the other parameters. NUM_BANKS is not constant on CIK.

This fixes 2D tiling for the display engine on CIK.

Signed-off-by: default avatarMarek Olšák <marek.olsak@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 35a90528

drivers/gpu/drm/radeon/atombios_crtc.c

+43 −21
Original line number Diff line number Diff line
@@ -1143,9 +1143,32 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 
	}



	if (tiling_flags & RADEON_TILING_MACRO) {

		if (rdev->family >= CHIP_BONAIRE)

			tmp = rdev->config.cik.tile_config;

		else if (rdev->family >= CHIP_TAHITI)

		evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);



		/* Set NUM_BANKS. */

		if (rdev->family >= CHIP_BONAIRE) {

			unsigned tileb, index, num_banks, tile_split_bytes;



			/* Calculate the macrotile mode index. */

			tile_split_bytes = 64 << tile_split;

			tileb = 8 * 8 * target_fb->bits_per_pixel / 8;

			tileb = min(tile_split_bytes, tileb);



			for (index = 0; tileb > 64; index++) {

				tileb >>= 1;

			}



			if (index >= 16) {

				DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",

					  target_fb->bits_per_pixel, tile_split);

				return -EINVAL;

			}



			num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;

			fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);

		} else {

			/* SI and older. */

			if (rdev->family >= CHIP_TAHITI)

				tmp = rdev->config.si.tile_config;

			else if (rdev->family >= CHIP_CAYMAN)

				tmp = rdev->config.cayman.tile_config;
@@ -1164,10 +1187,9 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 
				fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);

				break;

			}

		}



		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);



		evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);

		fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);

		fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);

		fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);