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Commit dbb42748 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Move the C3 LP write bit setup to gen3_init_clock_gating() for KMS 



Move the MI_ARB_STATE MI_ARB_C3_LP_WRITE_ENABLE setup to
gen3_init_clock_gating() from i915_gem_load() when KMS is enabled. Leave
it in i915_gem_load() for the UMS case, but add an explcit check, just
to make it easier to spot it when we eventually rip out UMS support.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 54e472ae

drivers/gpu/drm/i915/i915_gem.c

+1 −1
Original line number Diff line number Diff line
@@ -4756,7 +4756,7 @@ i915_gem_load(struct drm_device *dev) 
	init_waitqueue_head(&dev_priv->gpu_error.reset_queue);



	/* On GEN3 we really need to make sure the ARB C3 LP bit is set */

	if (IS_GEN3(dev)) {

	if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {

		I915_WRITE(MI_ARB_STATE,

			   _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));

	}

drivers/gpu/drm/i915/intel_pm.c

+3 −0
Original line number Diff line number Diff line
@@ -5507,6 +5507,9 @@ static void gen3_init_clock_gating(struct drm_device *dev) 


	/* interrupts should cause a wake up from C3 */

	I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));



	/* On GEN3 we really need to make sure the ARB C3 LP bit is set */

	I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));

}



static void i85x_init_clock_gating(struct drm_device *dev)