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Commit c2451d7f authored by Jesse Brandeburg's avatar Jesse Brandeburg Committed by Jeff Kirsher
Browse files

i40e/i40evf: fix rx descriptor status 



As reported by Eric Dumazet, the driver is not masking the right
bits in the receive descriptor before it starts checking them.

This patch extends the mask to allow for the right bits to be
checked, and fixes the issue permanently via a define.

CC: Eric Dumazet <eric.dumazet@gmail.com>
Change-ID: I3274f7619057a950f468143e6d7e11b129f54655
Signed-off-by: default avatarJesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent fff1f59b

drivers/net/ethernet/intel/i40e/i40e_type.h

+6 −4
Original line number Diff line number Diff line
@@ -492,9 +492,6 @@ union i40e_32byte_rx_desc { 
	} wb;  /* writeback */

};



#define I40E_RXD_QW1_STATUS_SHIFT	0

#define I40E_RXD_QW1_STATUS_MASK	(0x7FFFUL << I40E_RXD_QW1_STATUS_SHIFT)



enum i40e_rx_desc_status_bits {

	/* Note: These are predefined bit offsets */

	I40E_RX_DESC_STATUS_DD_SHIFT		= 0,
@@ -511,9 +508,14 @@ enum i40e_rx_desc_status_bits { 
	I40E_RX_DESC_STATUS_LPBK_SHIFT		= 14,

	I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT	= 15,

	I40E_RX_DESC_STATUS_RESERVED_SHIFT	= 16, /* 2 BITS */

	I40E_RX_DESC_STATUS_UDP_0_SHIFT		= 18

	I40E_RX_DESC_STATUS_UDP_0_SHIFT		= 18,

	I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */

};



#define I40E_RXD_QW1_STATUS_SHIFT	0

#define I40E_RXD_QW1_STATUS_MASK	(((1 << I40E_RX_DESC_STATUS_LAST) - 1) \

					 << I40E_RXD_QW1_STATUS_SHIFT)



#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT

#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK	(0x3UL << \

					     I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)

drivers/net/ethernet/intel/i40evf/i40e_type.h

+6 −4
Original line number Diff line number Diff line
@@ -492,9 +492,6 @@ union i40e_32byte_rx_desc { 
	} wb;  /* writeback */

};



#define I40E_RXD_QW1_STATUS_SHIFT	0

#define I40E_RXD_QW1_STATUS_MASK	(0x7FFFUL << I40E_RXD_QW1_STATUS_SHIFT)



enum i40e_rx_desc_status_bits {

	/* Note: These are predefined bit offsets */

	I40E_RX_DESC_STATUS_DD_SHIFT		= 0,
@@ -511,9 +508,14 @@ enum i40e_rx_desc_status_bits { 
	I40E_RX_DESC_STATUS_LPBK_SHIFT		= 14,

	I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT	= 15,

	I40E_RX_DESC_STATUS_RESERVED_SHIFT	= 16, /* 2 BITS */

	I40E_RX_DESC_STATUS_UDP_0_SHIFT		= 18

	I40E_RX_DESC_STATUS_UDP_0_SHIFT		= 18,

	I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */

};



#define I40E_RXD_QW1_STATUS_SHIFT	0

#define I40E_RXD_QW1_STATUS_MASK	(((1 << I40E_RX_DESC_STATUS_LAST) - 1) \

					 << I40E_RXD_QW1_STATUS_SHIFT)



#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT

#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK	(0x3UL << \

					     I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)