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Commit bb4278dc authored by Vikas Sajjan's avatar Vikas Sajjan Committed by Mike Turquette
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clk: samsung: Add set_rate() clk_ops for PLL36xx 



This patch adds set_rate and round_rate clk_ops for PLL36xx

Reviewed-by: default avatarTomasz Figa <t.figa@samsung.com>
Reviewed-by: default avatarDoug Anderson <dianders@chromium.org>
Signed-off-by: default avatarVikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent dfa89319

drivers/clk/samsung/clk-pll.c

+78 −1
Original line number Diff line number Diff line
@@ -160,6 +160,8 @@ static const struct clk_ops samsung_pll35xx_clk_min_ops = { 
/*

 * PLL36xx Clock Type

 */

/* Maximum lock time can be 3000 * PDIV cycles */

#define PLL36XX_LOCK_FACTOR    (3000)



#define PLL36XX_KDIV_MASK	(0xFFFF)

#define PLL36XX_MDIV_MASK	(0x1FF)
@@ -168,6 +170,8 @@ static const struct clk_ops samsung_pll35xx_clk_min_ops = { 
#define PLL36XX_MDIV_SHIFT	(16)

#define PLL36XX_PDIV_SHIFT	(8)

#define PLL36XX_SDIV_SHIFT	(0)

#define PLL36XX_KDIV_SHIFT	(0)

#define PLL36XX_LOCK_STAT_SHIFT	(29)



static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,

				unsigned long parent_rate)
@@ -191,8 +195,78 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, 
	return (unsigned long)fvco;

}



static inline bool samsung_pll36xx_mpk_change(

	const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1)

{

	u32 old_mdiv, old_pdiv, old_kdiv;



	old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;

	old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;

	old_kdiv = (pll_con1 >> PLL36XX_KDIV_SHIFT) & PLL36XX_KDIV_MASK;



	return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||

		rate->kdiv != old_kdiv);

}



static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,

					unsigned long parent_rate)

{

	struct samsung_clk_pll *pll = to_clk_pll(hw);

	u32 tmp, pll_con0, pll_con1;

	const struct samsung_pll_rate_table *rate;



	rate = samsung_get_pll_settings(pll, drate);

	if (!rate) {

		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,

			drate, __clk_get_name(hw->clk));

		return -EINVAL;

	}



	pll_con0 = __raw_readl(pll->con_reg);

	pll_con1 = __raw_readl(pll->con_reg + 4);



	if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) {

		/* If only s change, change just s value only*/

		pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);

		pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT);

		__raw_writel(pll_con0, pll->con_reg);



		return 0;

	}



	/* Set PLL lock time. */

	__raw_writel(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);



	 /* Change PLL PMS values */

	pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |

			(PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) |

			(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT));

	pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) |

			(rate->pdiv << PLL36XX_PDIV_SHIFT) |

			(rate->sdiv << PLL36XX_SDIV_SHIFT);

	__raw_writel(pll_con0, pll->con_reg);



	pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT);

	pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT;

	__raw_writel(pll_con1, pll->con_reg + 4);



	/* wait_lock_time */

	do {

		cpu_relax();

		tmp = __raw_readl(pll->con_reg);

	} while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT)));



	return 0;

}



static const struct clk_ops samsung_pll36xx_clk_ops = {

	.recalc_rate = samsung_pll36xx_recalc_rate,

	.set_rate = samsung_pll36xx_set_rate,

	.round_rate = samsung_pll_round_rate,

};



static const struct clk_ops samsung_pll36xx_clk_min_ops = {

	.recalc_rate = samsung_pll36xx_recalc_rate,

};



/*
@@ -493,6 +567,9 @@ static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk, 
	/* clk_ops for 36xx and 2650 are similar */

	case pll_36xx:

	case pll_2650:

		if (!pll->rate_table)

			init.ops = &samsung_pll36xx_clk_min_ops;

		else

			init.ops = &samsung_pll36xx_clk_ops;

		break;

	default: