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Commit b866d133 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon: add some additional 6xx/7xx/EG register init 



- SMX_SAR_CTL0 needs to be programmed correctly to prevent
problems with memory exports in certain cases.
- VC_ENHANCE needs to be initialized on 6xx/7xx.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 6b53a050

drivers/gpu/drm/radeon/evergreen.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -1932,6 +1932,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);

	smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);

	WREG32(SMX_DC_CTL0, smx_dc_ctl0);

	WREG32(SMX_DC_CTL0, smx_dc_ctl0);





	if (rdev->family <= CHIP_SUMO2)

		WREG32(SMX_SAR_CTL0, 0x00010000);



	WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |

	WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |

					POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |

					POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |

					SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));

					SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));

drivers/gpu/drm/radeon/evergreend.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -503,6 +503,7 @@ 
#define	SCRATCH_UMSK					0x8540

#define	SCRATCH_UMSK					0x8540

#define	SCRATCH_ADDR					0x8544

#define	SCRATCH_ADDR					0x8544





#define	SMX_SAR_CTL0					0xA008

#define	SMX_DC_CTL0					0xA020

#define	SMX_DC_CTL0					0xA020

#define		USE_HASH_FUNCTION				(1 << 0)

#define		USE_HASH_FUNCTION				(1 << 0)

#define		NUMBER_OF_SETS(x)				((x) << 1)

#define		NUMBER_OF_SETS(x)				((x) << 1)

drivers/gpu/drm/radeon/r600.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -1839,6 +1839,7 @@ void r600_gpu_init(struct radeon_device *rdev) 
	WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |

	WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |

			       NUM_CLIP_SEQ(3)));

			       NUM_CLIP_SEQ(3)));

	WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));

	WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));

	WREG32(VC_ENHANCE, 0);

}

}

drivers/gpu/drm/radeon/r600d.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -485,6 +485,7 @@ 
#define		TC_L2_SIZE(x)					((x)<<5)

#define		TC_L2_SIZE(x)					((x)<<5)

#define		L2_DISABLE_LATE_HIT				(1<<9)

#define		L2_DISABLE_LATE_HIT				(1<<9)





#define	VC_ENHANCE					0x9714





#define	VGT_CACHE_INVALIDATION				0x88C4

#define	VGT_CACHE_INVALIDATION				0x88C4

#define		CACHE_INVALIDATION(x)				((x)<<0)

#define		CACHE_INVALIDATION(x)				((x)<<0)

drivers/gpu/drm/radeon/rv770.c

+4 −1
Original line number Original line Diff line number Diff line
@@ -616,6 +616,9 @@ static void rv770_gpu_init(struct radeon_device *rdev) 
				       ACK_FLUSH_CTL(3) |

				       ACK_FLUSH_CTL(3) |

				       SYNC_FLUSH_CTL));

				       SYNC_FLUSH_CTL));





	if (rdev->family != CHIP_RV770)

		WREG32(SMX_SAR_CTL0, 0x00003f3f);



	db_debug3 = RREG32(DB_DEBUG3);

	db_debug3 = RREG32(DB_DEBUG3);

	db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);

	db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);

	switch (rdev->family) {

	switch (rdev->family) {
@@ -792,7 +795,7 @@ static void rv770_gpu_init(struct radeon_device *rdev) 




	WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |

	WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |

					  NUM_CLIP_SEQ(3)));

					  NUM_CLIP_SEQ(3)));



	WREG32(VC_ENHANCE, 0);

}

}





void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)

void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)