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Commit b7aee4bf authored by Paul Walmsley's avatar Paul Walmsley Committed by paul
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OMAP3 clock: use pr_debug() rather than pr_info() in some clock change code 



The CORE DPLL M2 frequency change code should use pr_debug(), not
pr_info(), for its debug messages.  Same with
omap2_clksel_round_rate_div().  While here, convert a few printk(KERN_ERR ..
into pr_err().

Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent 4519c2bf

arch/arm/mach-omap2/clock.c

+6 −6
Original line number Diff line number Diff line
@@ -547,7 +547,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 
	const struct clksel_rate *clkr;

	u32 last_div = 0;



	printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",

	pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",

		 clk->name, target_rate);



	*new_div = 1;
@@ -562,7 +562,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 


		/* Sanity check */

		if (clkr->div <= last_div)

			printk(KERN_ERR "clock: clksel_rate table not sorted "

			pr_err("clock: clksel_rate table not sorted "

			       "for clock %s", clk->name);



		last_div = clkr->div;
@@ -574,7 +574,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 
	}



	if (!clkr->div) {

		printk(KERN_ERR "clock: Could not find divisor for target "

		pr_err("clock: Could not find divisor for target "

		       "rate %ld for clock %s parent %s\n", target_rate,

		       clk->name, clk->parent->name);

		return ~0;
@@ -582,7 +582,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 


	*new_div = clkr->div;



	printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,

	pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,

		 (clk->parent->rate / clkr->div));



	return (clk->parent->rate / clkr->div);

arch/arm/mach-omap2/clock34xx.c

+4 −4
Original line number Diff line number Diff line
@@ -737,9 +737,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) 
		unlock_dll = 1;

	}



	pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,

	pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,

		 validrate);

	pr_info("clock: SDRC timing params used: %08x %08x %08x\n",

	pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",

		 sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);



	/* REVISIT: SRAM code doesn't support other M2 divisors yet */