Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit aa019b79 authored by Alex Deucher's avatar Alex Deucher Committed by Christian König
Browse files

drm/radeon/dp: check for errors in dpcd reads 



Check to make sure the transaction succeeded before
using the register value.  Fixes occasional link training
problems.

Noticed-by: default avatarSergei Antonov <saproj@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
parent 3b333c55

drivers/gpu/drm/radeon/atombios_dp.c

+25 −19
Original line number Diff line number Diff line
@@ -366,11 +366,11 @@ static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) 
	if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))

		return;



	if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3))

	if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)

		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",

			      buf[0], buf[1], buf[2]);



	if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3))

	if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)

		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",

			      buf[0], buf[1], buf[2]);

}
@@ -419,8 +419,8 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 


	if (dp_bridge != ENCODER_OBJECT_ID_NONE) {

		/* DP bridge chips */

		drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,

				  DP_EDP_CONFIGURATION_CAP, &tmp);

		if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,

				      DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {

			if (tmp & 1)

				panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;

			else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
@@ -428,13 +428,15 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 
				panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;

			else

				panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;

		}

	} else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {

		/* eDP */

		drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,

				  DP_EDP_CONFIGURATION_CAP, &tmp);

		if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,

				      DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {

			if (tmp & 1)

				panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;

		}

	}



	return panel_mode;

}
@@ -809,11 +811,15 @@ void radeon_dp_link_train(struct drm_encoder *encoder, 
	else

		dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;



	drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp);

	if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)

	    == 1) {

		if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))

			dp_info.tp3_supported = true;

		else

			dp_info.tp3_supported = false;

	} else {

		dp_info.tp3_supported = false;

	}



	memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);

	dp_info.rdev = rdev;