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Commit a885b3cc authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter
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drm/i915: Use the correct GMCH_CTRL register for Sandybridge+ 



The GMCH_CTRL register (or MGCC in the spec) is at a different address
on Sandybridge, and the address to which we currently write to is
undefined. These stray writes appear to upset (hard hang) my Ivybridge
machine whilst it is in UEFI mode.

Note that the register is still marked as locked RO on Sandybridge, so
vgaarb is still dysfunctional.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent be3d26b0

drivers/gpu/drm/i915/intel_display.c

+3 −2
Original line number Diff line number Diff line
@@ -11126,14 +11126,15 @@ void intel_connector_attach_encoder(struct intel_connector *connector, 
int intel_modeset_vga_set_state(struct drm_device *dev, bool state)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;

	u16 gmch_ctrl;



	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);

	pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl);

	if (state)

		gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;

	else

		gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;

	pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);

	pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl);

	return 0;

}