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Commit 9ef4e1d0 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: disable pll sharing for DP on DCE4.1 

Causes display problems.  We had already disabled
sharing for non-DP displays.

Based on a patch from:
Niels Ole Salscheider <niels_ole@salscheider-online.de>

bug:
https://bugzilla.kernel.org/show_bug.cgi?id=58121



Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 5e386b57

drivers/gpu/drm/radeon/atombios_crtc.c

+15 −1
Original line number Original line Diff line number Diff line
@@ -1774,6 +1774,20 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
			return ATOM_PPLL1;

			return ATOM_PPLL1;

		DRM_ERROR("unable to allocate a PPLL\n");

		DRM_ERROR("unable to allocate a PPLL\n");

		return ATOM_PPLL_INVALID;

		return ATOM_PPLL_INVALID;

	} else if (ASIC_IS_DCE41(rdev)) {

		/* Don't share PLLs on DCE4.1 chips */

		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {

			if (rdev->clock.dp_extclk)

				/* skip PPLL programming if using ext clock */

				return ATOM_PPLL_INVALID;

		}

		pll_in_use = radeon_get_pll_use_mask(crtc);

		if (!(pll_in_use & (1 << ATOM_PPLL1)))

			return ATOM_PPLL1;

		if (!(pll_in_use & (1 << ATOM_PPLL2)))

			return ATOM_PPLL2;

		DRM_ERROR("unable to allocate a PPLL\n");

		return ATOM_PPLL_INVALID;

	} else if (ASIC_IS_DCE4(rdev)) {

	} else if (ASIC_IS_DCE4(rdev)) {

		/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,

		/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,

		 * depending on the asic:

		 * depending on the asic:
@@ -1801,7 +1815,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) 
				if (pll != ATOM_PPLL_INVALID)

				if (pll != ATOM_PPLL_INVALID)

					return pll;

					return pll;

			}

			}

		} else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */

		} else {

			/* use the same PPLL for all monitors with the same clock */

			/* use the same PPLL for all monitors with the same clock */

			pll = radeon_get_shared_nondp_ppll(crtc);

			pll = radeon_get_shared_nondp_ppll(crtc);

			if (pll != ATOM_PPLL_INVALID)

			if (pll != ATOM_PPLL_INVALID)