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Commit 9eabb911 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-3.15' of git://people.freedesktop.org/~deathsimple/linux into drm-fixes 

this is the next pull quested for stashed up radeon fixes for 3.15. As discussed support for Mullins was separated out and will get it's own pull request. Remaining highlights are:
1. Some more patches to better handle PLL limits.
2. Making use of the PFLIP additional to the VBLANK interrupt, otherwise we sometimes miss page flip events.
3. Fix for the UVD command stream parser.
4. Fix for bootup UVD clocks on RV7xx systems.
5. Adding missing error check on dpcd reads.
6. Fixes number of banks calculation on SI.

* 'drm-fixes-3.15' of git://people.freedesktop.org/~deathsimple/linux:
  drm/radeon: lower the ref * post PLL maximum
  drm/radeon: check that we have a clock before PLL setup
  drm/radeon: drm/radeon: add missing radeon_semaphore_free to error path
  drm/radeon: Fix num_banks calculation for SI
  drm/radeon/dp: check for errors in dpcd reads
  drm/radeon: avoid high jitter with small frac divs
  drm/radeon: check buffer relocation offset
  drm/radeon: use pflip irq on R600+ v2
  drm/radeon/uvd: use lower clocks on old UVD to boot v2
parents 3cf0b031 cbe65513

drivers/gpu/drm/radeon/atombios_crtc.c

+34 −15
Original line number Diff line number Diff line
@@ -1177,16 +1177,18 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 


		/* Set NUM_BANKS. */

		if (rdev->family >= CHIP_TAHITI) {

			unsigned tileb, index, num_banks, tile_split_bytes;

			unsigned index, num_banks;



			if (rdev->family >= CHIP_BONAIRE) {

				unsigned tileb, tile_split_bytes;



				/* Calculate the macrotile mode index. */

				tile_split_bytes = 64 << tile_split;

				tileb = 8 * 8 * target_fb->bits_per_pixel / 8;

				tileb = min(tile_split_bytes, tileb);



			for (index = 0; tileb > 64; index++) {

				for (index = 0; tileb > 64; index++)

					tileb >>= 1;

			}



				if (index >= 16) {

					DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
@@ -1194,10 +1196,24 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 
					return -EINVAL;

				}



			if (rdev->family >= CHIP_BONAIRE)

				num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;

			else

			} else {

				switch (target_fb->bits_per_pixel) {

				case 8:

					index = 10;

					break;

				case 16:

					index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;

					break;

				default:

				case 32:

					index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;

					break;

				}



				num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;

			}



			fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);

		} else {

			/* NI and older. */
@@ -1885,6 +1901,9 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, 
	    (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))

		is_tvcv = true;



	if (!radeon_crtc->adjusted_clock)

		return -EINVAL;



	atombios_crtc_set_pll(crtc, adjusted_mode);



	if (ASIC_IS_DCE4(rdev))

drivers/gpu/drm/radeon/atombios_dp.c

+25 −19
Original line number Diff line number Diff line
@@ -366,11 +366,11 @@ static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) 
	if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))

		return;



	if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3))

	if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)

		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",

			      buf[0], buf[1], buf[2]);



	if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3))

	if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)

		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",

			      buf[0], buf[1], buf[2]);

}
@@ -419,8 +419,8 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 


	if (dp_bridge != ENCODER_OBJECT_ID_NONE) {

		/* DP bridge chips */

		drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,

				  DP_EDP_CONFIGURATION_CAP, &tmp);

		if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,

				      DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {

			if (tmp & 1)

				panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;

			else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
@@ -428,13 +428,15 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 
				panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;

			else

				panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;

		}

	} else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {

		/* eDP */

		drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,

				  DP_EDP_CONFIGURATION_CAP, &tmp);

		if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,

				      DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {

			if (tmp & 1)

				panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;

		}

	}



	return panel_mode;

}
@@ -809,11 +811,15 @@ void radeon_dp_link_train(struct drm_encoder *encoder, 
	else

		dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;



	drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp);

	if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)

	    == 1) {

		if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))

			dp_info.tp3_supported = true;

		else

			dp_info.tp3_supported = false;

	} else {

		dp_info.tp3_supported = false;

	}



	memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);

	dp_info.rdev = rdev;

drivers/gpu/drm/radeon/cik.c

+77 −0
Original line number Diff line number Diff line
@@ -3702,6 +3702,7 @@ int cik_copy_cpdma(struct radeon_device *rdev, 
	r = radeon_fence_emit(rdev, fence, ring->idx);

	if (r) {

		radeon_ring_unlock_undo(rdev, ring);

		radeon_semaphore_free(rdev, &sem, NULL);

		return r;

	}
@@ -6693,6 +6694,19 @@ static void cik_disable_interrupt_state(struct radeon_device *rdev) 
		WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);

		WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);

	}

	/* pflip */

	if (rdev->num_crtc >= 2) {

		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);

	}

	if (rdev->num_crtc >= 4) {

		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);

		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);

	}

	if (rdev->num_crtc >= 6) {

		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);

		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);

	}



	/* dac hotplug */

	WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
@@ -7049,6 +7063,25 @@ int cik_irq_set(struct radeon_device *rdev) 
		WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);

	}



	if (rdev->num_crtc >= 2) {

		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,

		       GRPH_PFLIP_INT_MASK);

		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,

		       GRPH_PFLIP_INT_MASK);

	}

	if (rdev->num_crtc >= 4) {

		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,

		       GRPH_PFLIP_INT_MASK);

		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,

		       GRPH_PFLIP_INT_MASK);

	}

	if (rdev->num_crtc >= 6) {

		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,

		       GRPH_PFLIP_INT_MASK);

		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,

		       GRPH_PFLIP_INT_MASK);

	}



	WREG32(DC_HPD1_INT_CONTROL, hpd1);

	WREG32(DC_HPD2_INT_CONTROL, hpd2);

	WREG32(DC_HPD3_INT_CONTROL, hpd3);
@@ -7085,6 +7118,29 @@ static inline void cik_irq_ack(struct radeon_device *rdev) 
	rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);

	rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);



	rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +

		EVERGREEN_CRTC0_REGISTER_OFFSET);

	rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +

		EVERGREEN_CRTC1_REGISTER_OFFSET);

	if (rdev->num_crtc >= 4) {

		rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +

			EVERGREEN_CRTC2_REGISTER_OFFSET);

		rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +

			EVERGREEN_CRTC3_REGISTER_OFFSET);

	}

	if (rdev->num_crtc >= 6) {

		rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +

			EVERGREEN_CRTC4_REGISTER_OFFSET);

		rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +

			EVERGREEN_CRTC5_REGISTER_OFFSET);

	}



	if (rdev->irq.stat_regs.cik.d1grph_int & GRPH_PFLIP_INT_OCCURRED)

		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,

		       GRPH_PFLIP_INT_CLEAR);

	if (rdev->irq.stat_regs.cik.d2grph_int & GRPH_PFLIP_INT_OCCURRED)

		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,

		       GRPH_PFLIP_INT_CLEAR);

	if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)

		WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);

	if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)
@@ -7095,6 +7151,12 @@ static inline void cik_irq_ack(struct radeon_device *rdev) 
		WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);



	if (rdev->num_crtc >= 4) {

		if (rdev->irq.stat_regs.cik.d3grph_int & GRPH_PFLIP_INT_OCCURRED)

			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,

			       GRPH_PFLIP_INT_CLEAR);

		if (rdev->irq.stat_regs.cik.d4grph_int & GRPH_PFLIP_INT_OCCURRED)

			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,

			       GRPH_PFLIP_INT_CLEAR);

		if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)

			WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);

		if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
@@ -7106,6 +7168,12 @@ static inline void cik_irq_ack(struct radeon_device *rdev) 
	}



	if (rdev->num_crtc >= 6) {

		if (rdev->irq.stat_regs.cik.d5grph_int & GRPH_PFLIP_INT_OCCURRED)

			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,

			       GRPH_PFLIP_INT_CLEAR);

		if (rdev->irq.stat_regs.cik.d6grph_int & GRPH_PFLIP_INT_OCCURRED)

			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,

			       GRPH_PFLIP_INT_CLEAR);

		if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)

			WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);

		if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
@@ -7457,6 +7525,15 @@ restart_ih: 
				break;

			}

			break;

		case 8: /* D1 page flip */

		case 10: /* D2 page flip */

		case 12: /* D3 page flip */

		case 14: /* D4 page flip */

		case 16: /* D5 page flip */

		case 18: /* D6 page flip */

			DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1);

			radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1);

			break;

		case 42: /* HPD hotplug */

			switch (src_data) {

			case 0:

drivers/gpu/drm/radeon/cik_sdma.c

+1 −0
Original line number Diff line number Diff line
@@ -562,6 +562,7 @@ int cik_copy_dma(struct radeon_device *rdev, 
	r = radeon_fence_emit(rdev, fence, ring->idx);

	if (r) {

		radeon_ring_unlock_undo(rdev, ring);

		radeon_semaphore_free(rdev, &sem, NULL);

		return r;

	}

drivers/gpu/drm/radeon/cikd.h

+9 −0
Original line number Diff line number Diff line
@@ -888,6 +888,15 @@ 
#       define DC_HPD6_RX_INTERRUPT                     (1 << 18)

#define DISP_INTERRUPT_STATUS_CONTINUE6                 0x6780



/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */

#define GRPH_INT_STATUS                                 0x6858

#       define GRPH_PFLIP_INT_OCCURRED                  (1 << 0)

#       define GRPH_PFLIP_INT_CLEAR                     (1 << 8)

/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */

#define GRPH_INT_CONTROL                                0x685c

#       define GRPH_PFLIP_INT_MASK                      (1 << 0)

#       define GRPH_PFLIP_INT_TYPE                      (1 << 8)



#define	DAC_AUTODETECT_INT_CONTROL			0x67c8



#define DC_HPD1_INT_STATUS                              0x601c