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Commit 8e9356c6 authored by Max Filippov's avatar Max Filippov
Browse files

xtensa: fsf: drop nonexistent GPIO32 support 



The toolchain for xtensa FSF core never supported GPIO32, drop it on the
linux side too.

Reported-by: default avatarFengguang Wu <fengguang.wu@intel.com>
Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
Acked-by: default avatarBaruch Siach <baruch@tkos.co.il>
parent e9d6dca5

arch/xtensa/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -80,7 +80,6 @@ choice 
config XTENSA_VARIANT_FSF

	bool "fsf - default (not generic) configuration"

	select MMU

	select HAVE_XTENSA_GPIO32



config XTENSA_VARIANT_DC232B

	bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"

arch/xtensa/variants/fsf/include/variant/tie.h

+2 −7
Original line number Diff line number Diff line
@@ -18,13 +18,6 @@ 
#define XCHAL_CP_MASK			0x00	/* bitmask of all CPs by ID */

#define XCHAL_CP_PORT_MASK		0x00	/* bitmask of only port CPs */



/*  Basic parameters of each coprocessor:  */

#define XCHAL_CP7_NAME			"XTIOP"

#define XCHAL_CP7_IDENT			XTIOP

#define XCHAL_CP7_SA_SIZE		0	/* size of state save area */

#define XCHAL_CP7_SA_ALIGN		1	/* min alignment of save area */

#define XCHAL_CP_ID_XTIOP		7	/* coprocessor ID (0..7) */



/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */

#define XCHAL_NCP_SA_SIZE		0

#define XCHAL_NCP_SA_ALIGN		1
@@ -42,6 +35,8 @@ 
#define XCHAL_CP5_SA_ALIGN		1

#define XCHAL_CP6_SA_SIZE		0

#define XCHAL_CP6_SA_ALIGN		1

#define XCHAL_CP7_SA_SIZE		0

#define XCHAL_CP7_SA_ALIGN		1



/*  Save area for non-coprocessor optional and custom (TIE) state:  */

#define XCHAL_NCP_SA_SIZE		0