Merge branch 'omap-clock-upstream' of git://git.pwsan.com/linux-2.6 into for-next (88b6f7eb) · Commits · e / devices / android_kernel_samsung_universal8890

arch/arm/mach-omap1/clock.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -776,7 +776,7 @@ int __init omap1_clk_init(void)
		arm_idlect1_mask = ~0;

		for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
		clk_init_one(c->lk.clk);
		clk_preinit(c->lk.clk);

		cpu_mask = 0;
		if (cpu_is_omap16xx())

arch/arm/mach-omap2/clock.c

+7 −7

Original line number	Diff line number	Diff line
		@@ -547,7 +547,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
		const struct clksel_rate *clkr;
		u32 last_div = 0;

		printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
		pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
		clk->name, target_rate);

		*new_div = 1;
		@@ -562,7 +562,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,

		/* Sanity check */
		if (clkr->div <= last_div)
		printk(KERN_ERR "clock: clksel_rate table not sorted "
		pr_err("clock: clksel_rate table not sorted "
		"for clock %s", clk->name);

		last_div = clkr->div;
		@@ -574,7 +574,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
		}

		if (!clkr->div) {
		printk(KERN_ERR "clock: Could not find divisor for target "
		pr_err("clock: Could not find divisor for target "
		"rate %ld for clock %s parent %s\n", target_rate,
		clk->name, clk->parent->name);
		return ~0;
		@@ -582,7 +582,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,

		*new_div = clkr->div;

		printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
		pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
		(clk->parent->rate / clkr->div));

		return (clk->parent->rate / clkr->div);
		@@ -1035,7 +1035,7 @@ void omap2_clk_disable_unused(struct clk *clk)
		if ((regval32 & (1 << clk->enable_bit)) == v)
		return;

		printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
		printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name);
		if (cpu_is_omap34xx()) {
		omap2_clk_enable(clk);
		omap2_clk_disable(clk);

arch/arm/mach-omap2/clock24xx.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -725,7 +725,7 @@ int __init omap2_clk_init(void)
		clk_init(&omap2_clk_functions);

		for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
		clk_init_one(c->lk.clk);
		clk_preinit(c->lk.clk);

		osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
		propagate_rate(&osc_ck);

arch/arm/mach-omap2/clock34xx.c

+14 −6

Original line number	Diff line number	Diff line
		@@ -281,6 +281,8 @@ static struct omap_clk omap34xx_clks[] = {

		#define MAX_DPLL_WAIT_TRIES 1000000

		#define MIN_SDRC_DLL_LOCK_FREQ 83000000

		/**
		* omap3_dpll_recalc - recalculate DPLL rate
		* @clk: DPLL struct clk
		@@ -703,6 +705,7 @@ static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
		static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
		{
		u32 new_div = 0;
		u32 unlock_dll = 0;
		unsigned long validrate, sdrcrate;
		struct omap_sdrc_params *sp;

		@@ -729,9 +732,14 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
		if (!sp)
		return -EINVAL;

		pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
		if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
		pr_debug("clock: will unlock SDRC DLL\n");
		unlock_dll = 1;
		}

		pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
		validrate);
		pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
		pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
		sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);

		/* REVISIT: SRAM code doesn't support other M2 divisors yet */
		@@ -739,7 +747,7 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)

		/* REVISIT: Add SDRC_MR changing to this code also */
		omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
		sp->actim_ctrlb, new_div);
		sp->actim_ctrlb, new_div, unlock_dll);

		return 0;
		}
		@@ -956,7 +964,7 @@ int __init omap2_clk_init(void)
		clk_init(&omap2_clk_functions);

		for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
		clk_init_one(c->lk.clk);
		clk_preinit(c->lk.clk);

		for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
		if (c->cpu & cpu_clkflg) {

arch/arm/mach-omap2/sdrc.c

+18 −1

Original line number	Diff line number	Diff line
		@@ -37,6 +37,10 @@ static struct omap_sdrc_params *sdrc_init_params;
		void __iomem *omap2_sdrc_base;
		void __iomem *omap2_sms_base;

		/* SDRC_POWER register bits */
		#define SDRC_POWER_EXTCLKDIS_SHIFT 3
		#define SDRC_POWER_PWDENA_SHIFT 2
		#define SDRC_POWER_PAGEPOLICY_SHIFT 0

		/**
		* omap2_sdrc_get_params - return SDRC register values for a given clock rate
		@@ -74,7 +78,14 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
		omap2_sms_base = omap2_globals->sms;
		}

		/* turn on smart idle modes for SDRAM scheduler and controller */
		/**
		* omap2_sdrc_init - initialize SMS, SDRC devices on boot
		* @sp: pointer to a null-terminated list of struct omap_sdrc_params
		*
		* Turn on smart idle modes for SDRAM scheduler and controller.
		* Program a known-good configuration for the SDRC to deal with buggy
		* bootloaders.
		*/
		void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
		{
		u32 l;
		@@ -90,4 +101,10 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
		sdrc_write_reg(l, SDRC_SYSCONFIG);

		sdrc_init_params = sp;

		/* XXX Enable SRFRONIDLEREQ here also? */
		l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) \|
		(1 << SDRC_POWER_PWDENA_SHIFT) \|
		(1 << SDRC_POWER_PAGEPOLICY_SHIFT);
		sdrc_write_reg(l, SDRC_POWER);
		}