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Commit 87b3c6ef authored by Kukjin Kim's avatar Kukjin Kim
Browse files

ARM: EXYNOS: add clock part for EXYNOS5250 SoC 



This patch adds clock-exynos5.c for EXYNOS5250 now
and that can be used for other EXYNOS5 SoCs later.

Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 920f4880

arch/arm/mach-exynos/clock-exynos5.c

0 → 100644
+1247 −0

File added.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-exynos/include/mach/regs-clock.h

+62 −0
Original line number Diff line number Diff line
@@ -253,6 +253,68 @@ 
#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT		(0)

#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK		(0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)



/* For EXYNOS5250 */



#define EXYNOS5_APLL_CON0			EXYNOS_CLKREG(0x00100)

#define EXYNOS5_CLKSRC_CPU			EXYNOS_CLKREG(0x00200)

#define EXYNOS5_CLKDIV_CPU0			EXYNOS_CLKREG(0x00500)

#define EXYNOS5_MPLL_CON0			EXYNOS_CLKREG(0x04100)

#define EXYNOS5_CLKSRC_CORE1			EXYNOS_CLKREG(0x04204)



#define EXYNOS5_CLKGATE_IP_CORE			EXYNOS_CLKREG(0x04900)



#define EXYNOS5_CLKDIV_ACP			EXYNOS_CLKREG(0x08500)



#define EXYNOS5_CLKSRC_TOP2			EXYNOS_CLKREG(0x10218)

#define EXYNOS5_EPLL_CON0			EXYNOS_CLKREG(0x10130)

#define EXYNOS5_EPLL_CON1			EXYNOS_CLKREG(0x10134)

#define EXYNOS5_VPLL_CON0			EXYNOS_CLKREG(0x10140)

#define EXYNOS5_VPLL_CON1			EXYNOS_CLKREG(0x10144)

#define EXYNOS5_CPLL_CON0			EXYNOS_CLKREG(0x10120)



#define EXYNOS5_CLKSRC_TOP0			EXYNOS_CLKREG(0x10210)

#define EXYNOS5_CLKSRC_TOP3			EXYNOS_CLKREG(0x1021C)

#define EXYNOS5_CLKSRC_GSCL			EXYNOS_CLKREG(0x10220)

#define EXYNOS5_CLKSRC_DISP1_0			EXYNOS_CLKREG(0x1022C)

#define EXYNOS5_CLKSRC_FSYS			EXYNOS_CLKREG(0x10244)

#define EXYNOS5_CLKSRC_PERIC0			EXYNOS_CLKREG(0x10250)



#define EXYNOS5_CLKSRC_MASK_TOP			EXYNOS_CLKREG(0x10310)

#define EXYNOS5_CLKSRC_MASK_GSCL		EXYNOS_CLKREG(0x10320)

#define EXYNOS5_CLKSRC_MASK_DISP1_0		EXYNOS_CLKREG(0x1032C)

#define EXYNOS5_CLKSRC_MASK_FSYS		EXYNOS_CLKREG(0x10340)

#define EXYNOS5_CLKSRC_MASK_PERIC0		EXYNOS_CLKREG(0x10350)



#define EXYNOS5_CLKDIV_TOP0			EXYNOS_CLKREG(0x10510)

#define EXYNOS5_CLKDIV_TOP1			EXYNOS_CLKREG(0x10514)

#define EXYNOS5_CLKDIV_GSCL			EXYNOS_CLKREG(0x10520)

#define EXYNOS5_CLKDIV_DISP1_0			EXYNOS_CLKREG(0x1052C)

#define EXYNOS5_CLKDIV_GEN			EXYNOS_CLKREG(0x1053C)

#define EXYNOS5_CLKDIV_FSYS0			EXYNOS_CLKREG(0x10548)

#define EXYNOS5_CLKDIV_FSYS1			EXYNOS_CLKREG(0x1054C)

#define EXYNOS5_CLKDIV_FSYS2			EXYNOS_CLKREG(0x10550)

#define EXYNOS5_CLKDIV_FSYS3			EXYNOS_CLKREG(0x10554)

#define EXYNOS5_CLKDIV_PERIC0			EXYNOS_CLKREG(0x10558)



#define EXYNOS5_CLKGATE_IP_ACP			EXYNOS_CLKREG(0x08800)

#define EXYNOS5_CLKGATE_IP_GSCL			EXYNOS_CLKREG(0x10920)

#define EXYNOS5_CLKGATE_IP_DISP1		EXYNOS_CLKREG(0x10928)

#define EXYNOS5_CLKGATE_IP_MFC			EXYNOS_CLKREG(0x1092C)

#define EXYNOS5_CLKGATE_IP_GEN			EXYNOS_CLKREG(0x10934)

#define EXYNOS5_CLKGATE_IP_FSYS			EXYNOS_CLKREG(0x10944)

#define EXYNOS5_CLKGATE_IP_GPS			EXYNOS_CLKREG(0x1094C)

#define EXYNOS5_CLKGATE_IP_PERIC		EXYNOS_CLKREG(0x10950)

#define EXYNOS5_CLKGATE_IP_PERIS		EXYNOS_CLKREG(0x10960)

#define EXYNOS5_CLKGATE_BLOCK			EXYNOS_CLKREG(0x10980)



#define EXYNOS5_BPLL_CON0			EXYNOS_CLKREG(0x20110)

#define EXYNOS5_CLKSRC_CDREX			EXYNOS_CLKREG(0x20200)

#define EXYNOS5_CLKDIV_CDREX			EXYNOS_CLKREG(0x20500)



#define EXYNOS5_EPLL_LOCK			EXYNOS_CLKREG(0x10030)



#define EXYNOS5_EPLLCON0_LOCKED_SHIFT		(29)



/* Compatibility defines and inclusion */



#include <mach/regs-pmu.h>

arch/arm/plat-s5p/clock.c

+36 −0
Original line number Diff line number Diff line
@@ -61,6 +61,20 @@ struct clk clk_fout_apll = { 
	.id		= -1,

};



/* BPLL clock output */



struct clk clk_fout_bpll = {

	.name		= "fout_bpll",

	.id		= -1,

};



/* CPLL clock output */



struct clk clk_fout_cpll = {

	.name		= "fout_cpll",

	.id		= -1,

};



/* MPLL clock output

 * No need .ctrlbit, this is always on

*/
@@ -101,6 +115,28 @@ struct clksrc_sources clk_src_apll = { 
	.nr_sources	= ARRAY_SIZE(clk_src_apll_list),

};



/* Possible clock sources for BPLL Mux */

static struct clk *clk_src_bpll_list[] = {

	[0] = &clk_fin_bpll,

	[1] = &clk_fout_bpll,

};



struct clksrc_sources clk_src_bpll = {

	.sources	= clk_src_bpll_list,

	.nr_sources	= ARRAY_SIZE(clk_src_bpll_list),

};



/* Possible clock sources for CPLL Mux */

static struct clk *clk_src_cpll_list[] = {

	[0] = &clk_fin_cpll,

	[1] = &clk_fout_cpll,

};



struct clksrc_sources clk_src_cpll = {

	.sources	= clk_src_cpll_list,

	.nr_sources	= ARRAY_SIZE(clk_src_cpll_list),

};



/* Possible clock sources for MPLL Mux */

static struct clk *clk_src_mpll_list[] = {

	[0] = &clk_fin_mpll,

arch/arm/plat-samsung/include/plat/s5p-clock.h

+6 −0
Original line number Diff line number Diff line
@@ -18,6 +18,8 @@ 
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)



#define clk_fin_apll clk_ext_xtal_mux

#define clk_fin_bpll clk_ext_xtal_mux

#define clk_fin_cpll clk_ext_xtal_mux

#define clk_fin_mpll clk_ext_xtal_mux

#define clk_fin_epll clk_ext_xtal_mux

#define clk_fin_dpll clk_ext_xtal_mux
@@ -29,6 +31,8 @@ extern struct clk clk_xusbxti; 
extern struct clk clk_48m;

extern struct clk s5p_clk_27m;

extern struct clk clk_fout_apll;

extern struct clk clk_fout_bpll;

extern struct clk clk_fout_cpll;

extern struct clk clk_fout_mpll;

extern struct clk clk_fout_epll;

extern struct clk clk_fout_dpll;
@@ -37,6 +41,8 @@ extern struct clk clk_arm; 
extern struct clk clk_vpll;



extern struct clksrc_sources clk_src_apll;

extern struct clksrc_sources clk_src_bpll;

extern struct clksrc_sources clk_src_cpll;

extern struct clksrc_sources clk_src_mpll;

extern struct clksrc_sources clk_src_epll;

extern struct clksrc_sources clk_src_dpll;