Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 86239ceb authored by Len Brown's avatar Len Brown
Browse files

intel_idle: initial C8, C9, C10 support 



Allow intel_idle and cpuidle to utilize C8, C9, C10
when they are present on...
"Fourth Generation Intel(R) Core(TM) Processors",
which are based on Intel(R) microarchitecture code name Haswell.

Signed-off-by: default avatarLen Brown <len.brown@intel.com>
parent ca58710f

drivers/idle/intel_idle.c

+21 −0
Original line number Diff line number Diff line
@@ -273,6 +273,27 @@ static struct cpuidle_state hsw_cstates[CPUIDLE_STATE_MAX] = { 
		.exit_latency = 166,

		.target_residency = 500,

		.enter = &intel_idle },

	{

		.name = "C8-HSW",

		.desc = "MWAIT 0x40",

		.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 300,

		.target_residency = 900,

		.enter = &intel_idle },

	{

		.name = "C9-HSW",

		.desc = "MWAIT 0x50",

		.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 600,

		.target_residency = 1800,

		.enter = &intel_idle },

	{

		.name = "C10-HSW",

		.desc = "MWAIT 0x60",

		.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 2600,

		.target_residency = 7700,

		.enter = &intel_idle },

	{

		.enter = NULL }

};

include/linux/cpuidle.h

+1 −1
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 
#include <linux/completion.h>

#include <linux/hrtimer.h>



#define CPUIDLE_STATE_MAX	8

#define CPUIDLE_STATE_MAX	10

#define CPUIDLE_NAME_LEN	16

#define CPUIDLE_DESC_LEN	32