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Commit 80a74f7f authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: Drop dev from pte_encode 



The original pte_encode function needed the dev argument so we could do
platform specific handling via IS_GENX, etc. With the merging of a pte
encoding function there should never been a need to quirk away gen
specific details.

The patch doesn't do much but makes the upcoming reworks in gtt/ppgtt/mm
slightly (albeit, ever so) easier.

Reviewed-by: default avatarKenneth Graunke <kenneth@whitecape.org>
Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 67167240

drivers/gpu/drm/i915/i915_drv.h

+2 −4
Original line number Diff line number Diff line
@@ -482,8 +482,7 @@ struct i915_gtt { 
				   struct sg_table *st,

				   unsigned int pg_start,

				   enum i915_cache_level cache_level);

	gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,

				     dma_addr_t addr,

	gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,

				     enum i915_cache_level level);

};

#define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
@@ -503,8 +502,7 @@ struct i915_hw_ppgtt { 
			       struct sg_table *st,

			       unsigned int pg_start,

			       enum i915_cache_level cache_level);

	gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,

				     dma_addr_t addr,

	gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,

				     enum i915_cache_level level);

	int (*enable)(struct drm_device *dev);

	void (*cleanup)(struct i915_hw_ppgtt *ppgtt);

drivers/gpu/drm/i915/i915_gem_gtt.c

+8 −13
Original line number Diff line number Diff line
@@ -45,8 +45,7 @@ 
#define GEN6_PTE_CACHE_LLC_MLC		(3 << 1)

#define GEN6_PTE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)



static gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev,

				      dma_addr_t addr,

static gen6_gtt_pte_t gen6_pte_encode(dma_addr_t addr,

				      enum i915_cache_level level)

{

	gen6_gtt_pte_t pte = GEN6_PTE_VALID;
@@ -72,8 +71,7 @@ static gen6_gtt_pte_t gen6_pte_encode(struct drm_device *dev, 
#define BYT_PTE_WRITEABLE		(1 << 1)

#define BYT_PTE_SNOOPED_BY_CPU_CACHES	(1 << 2)



static gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev,

				     dma_addr_t addr,

static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,

				     enum i915_cache_level level)

{

	gen6_gtt_pte_t pte = GEN6_PTE_VALID;
@@ -90,8 +88,7 @@ static gen6_gtt_pte_t byt_pte_encode(struct drm_device *dev, 
	return pte;

}



static gen6_gtt_pte_t hsw_pte_encode(struct drm_device *dev,

				     dma_addr_t addr,

static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,

				     enum i915_cache_level level)

{

	gen6_gtt_pte_t pte = GEN6_PTE_VALID;
@@ -194,8 +191,7 @@ static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt, 
	unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;

	unsigned last_pte, i;



	scratch_pte = ppgtt->pte_encode(ppgtt->dev,

					dev_priv->gtt.scratch.addr,

	scratch_pte = ppgtt->pte_encode(dev_priv->gtt.scratch.addr,

					I915_CACHE_LLC);



	while (num_entries) {
@@ -231,8 +227,7 @@ static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt, 
		dma_addr_t page_addr;



		page_addr = sg_page_iter_dma_address(&sg_iter);

		pt_vaddr[act_pte] = ppgtt->pte_encode(ppgtt->dev, page_addr,

						      cache_level);

		pt_vaddr[act_pte] = ppgtt->pte_encode(page_addr, cache_level);

		if (++act_pte == I915_PPGTT_PT_ENTRIES) {

			kunmap_atomic(pt_vaddr);

			act_pt++;
@@ -483,7 +478,7 @@ static void gen6_ggtt_insert_entries(struct drm_device *dev, 


	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {

		addr = sg_page_iter_dma_address(&sg_iter);

		iowrite32(dev_priv->gtt.pte_encode(dev, addr, level),

		iowrite32(dev_priv->gtt.pte_encode(addr, level),

			  &gtt_entries[i]);

		i++;

	}
@@ -496,7 +491,7 @@ static void gen6_ggtt_insert_entries(struct drm_device *dev, 
	 */

	if (i != 0)

		WARN_ON(readl(&gtt_entries[i-1])

			!= dev_priv->gtt.pte_encode(dev, addr, level));

			!= dev_priv->gtt.pte_encode(addr, level));



	/* This next bit makes the above posting read even more important. We

	 * want to flush the TLBs only after we're certain all the PTE updates
@@ -521,7 +516,7 @@ static void gen6_ggtt_clear_range(struct drm_device *dev, 
		 first_entry, num_entries, max_entries))

		num_entries = max_entries;



	scratch_pte = dev_priv->gtt.pte_encode(dev, dev_priv->gtt.scratch.addr,

	scratch_pte = dev_priv->gtt.pte_encode(dev_priv->gtt.scratch.addr,

					       I915_CACHE_LLC);

	for (i = 0; i < num_entries; i++)

		iowrite32(scratch_pte, &gtt_base[i]);