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Commit 7f081f17 authored by Deng-Cheng Zhu's avatar Deng-Cheng Zhu Committed by Ralf Baechle
Browse files

MIPS: Perf: Fix 74K cache map 



According to Software User's Manual, the event of last-level-cache
read/write misses is mapped to even counters. Odd counters of that
event number count miss cycles.

Signed-off-by: default avatarDeng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6036/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 959f5854

arch/mips/kernel/perf_event_mipsxx.c

+2 −2
Original line number Diff line number Diff line
@@ -971,11 +971,11 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map 
[C(LL)] = {

	[C(OP_READ)] = {

		[C(RESULT_ACCESS)]	= { 0x1c, CNTR_ODD, P },

		[C(RESULT_MISS)]	= { 0x1d, CNTR_EVEN | CNTR_ODD, P },

		[C(RESULT_MISS)]	= { 0x1d, CNTR_EVEN, P },

	},

	[C(OP_WRITE)] = {

		[C(RESULT_ACCESS)]	= { 0x1c, CNTR_ODD, P },

		[C(RESULT_MISS)]	= { 0x1d, CNTR_EVEN | CNTR_ODD, P },

		[C(RESULT_MISS)]	= { 0x1d, CNTR_EVEN, P },

	},

},

[C(ITLB)] = {