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Commit 7c6035b6 authored by Amit Daniel Kachhap's avatar Amit Daniel Kachhap Committed by Kukjin Kim
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ARM: S5P: add L2 early resume code 



This patch adds code to resume L2 before MMU is enabled in
suspend and cpuidle resume paths. s3c_cpu_resume is moved to the
data section with appropriate comments.

Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: default avatarAmit Daniel Kachhap <amit.kachhap@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 67173ca4

arch/arm/plat-s5p/sleep.S

+38 −6
Original line number Diff line number Diff line
@@ -23,9 +23,18 @@ 
*/



#include <linux/linkage.h>

#include <asm/assembler.h>

#include <asm/asm-offsets.h>

#include <asm/hardware/cache-l2x0.h>



	.text

/*

 *	 The following code is located into the .data section. This is to

 *	 allow l2x0_regs_phys to be accessed with a relative load while we

 *	 can't rely on any MMU translation. We could have put l2x0_regs_phys

 *	 in the .text section as well, but some setups might insist on it to

 *	 be truly read-only. (Reference from: arch/arm/kernel/sleep.S)

 */

	.data

	.align



	/*

	 * sleep magic, to allow the bootloader to check for an valid
@@ -39,11 +48,34 @@ 
	 * s3c_cpu_resume

	 *

	 * resume code entry for bootloader to call

	 *

	 * we must put this code here in the data segment as we have no

	 * other way of restoring the stack pointer after sleep, and we

	 * must not write to the code segment (code is read-only)

	 */



ENTRY(s3c_cpu_resume)

#ifdef CONFIG_CACHE_L2X0

	adr	r0, l2x0_regs_phys

	ldr	r0, [r0]

	ldr	r1, [r0, #L2X0_R_PHY_BASE]

	ldr	r2, [r1, #L2X0_CTRL]

	tst	r2, #0x1

	bne	resume_l2on

	ldr	r2, [r0, #L2X0_R_AUX_CTRL]

	str	r2, [r1, #L2X0_AUX_CTRL]

	ldr	r2, [r0, #L2X0_R_TAG_LATENCY]

	str	r2, [r1, #L2X0_TAG_LATENCY_CTRL]

	ldr	r2, [r0, #L2X0_R_DATA_LATENCY]

	str	r2, [r1, #L2X0_DATA_LATENCY_CTRL]

	ldr	r2, [r0, #L2X0_R_PREFETCH_CTRL]

	str	r2, [r1, #L2X0_PREFETCH_CTRL]

	ldr	r2, [r0, #L2X0_R_PWR_CTRL]

	str	r2, [r1, #L2X0_POWER_CTRL]

	mov	r2, #1

	str	r2, [r1, #L2X0_CTRL]

resume_l2on:

#endif

	b	cpu_resume

ENDPROC(s3c_cpu_resume)

#ifdef CONFIG_CACHE_L2X0

	.globl l2x0_regs_phys

l2x0_regs_phys:

	.long	0

#endif