Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7550cfab authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pci-v3.16-changes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 

Pull more PCI updates from Bjorn Helgaas:
 "Here are some more things I'd like to see in v3.16-rc1:

   - DMA alias iterator, part of some work to fix IOMMU issues
   - MVEBU, Tegra, DesignWare changes that I forgot to include before
   - Some whitespace code cleanup

  Details:

  IOMMU
    - Add DMA alias iterator (Alex Williamson)
    - Add DMA alias quirks for ASMedia, ITE, Tundra bridges (Alex Williamson)
    - Add DMA alias quirks for Marvell, Ricoh devices (Alex Williamson)
    - Add DMA alias quirk for HighPoint devices (Jérôme Carretero)

  MSI
    - Fix leak in free_msi_irqs() (Alexei Starovoitov)

  Marvell MVEBU
    - Remove unnecessary use of 'conf_lock' spinlock (Andrew Murray)
    - Avoid setting an undefined window size (Jason Gunthorpe)
    - Allow several windows with the same target/attribute (Thomas Petazzoni)
    - Split PCIe BARs into multiple MBus windows when needed (Thomas Petazzoni)
    - Fix off-by-one in the computed size of the mbus windows (Willy Tarreau)

  NVIDIA Tegra
    - Use new OF interrupt mapping when possible (Lucas Stach)

  Synopsys DesignWare
    - Remove unnecessary use of 'conf_lock' spinlock (Andrew Murray)
    - Use new OF interrupt mapping when possible (Lucas Stach)
    - Split Exynos and i.MX bindings (Lucas Stach)
    - Fix comment for setting number of lanes (Mohit Kumar)
    - Fix iATU programming for cfg1, io and mem viewport (Mohit Kumar)

  Miscellaneous
    - EXPORT_SYMBOL cleanup (Ryan Desfosses)
    - Whitespace cleanup (Ryan Desfosses)
    - Merge multi-line quoted strings (Ryan Desfosses)"

* tag 'pci-v3.16-changes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (21 commits)
  PCI: Add function 1 DMA alias quirk for HighPoint RocketRaid 642L
  PCI/MSI: Fix memory leak in free_msi_irqs()
  PCI: Merge multi-line quoted strings
  PCI: Whitespace cleanup
  PCI: Move EXPORT_SYMBOL so it immediately follows function/variable
  PCI: Add bridge DMA alias quirk for ITE bridge
  PCI: designware: Split Exynos and i.MX bindings
  PCI: Add bridge DMA alias quirk for ASMedia and Tundra bridges
  PCI: Add support for PCIe-to-PCI bridge DMA alias quirks
  PCI: Add function 1 DMA alias quirk for Marvell devices
  PCI: Add function 0 DMA alias quirk for Ricoh devices
  PCI: Add support for DMA alias quirks
  PCI: Convert pci_dev_flags definitions to bit shifts
  PCI: Add DMA alias iterator
  PCI: mvebu: Use '%pa' for printing 'phys_addr_t' type
  PCI: mvebu: Remove unnecessary use of 'conf_lock' spinlock
  PCI: designware: Remove unnecessary use of 'conf_lock' spinlock
  PCI: designware: Use new OF interrupt mapping when possible
  PCI: designware: Fix iATU programming for cfg1, io and mem viewport
  PCI: designware: Fix comment for setting number of lanes
  ...
parents 19c1940f 38a61482

Documentation/devicetree/bindings/pci/designware-pcie.txt

+6 −68
Original line number Diff line number Diff line 
* Synopsys Designware PCIe interface



Required properties:

- compatible: should contain "snps,dw-pcie" to identify the

	core, plus an identifier for the specific instance, such

	as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie".

- reg: base addresses and lengths of the pcie controller,

	the phy controller, additional register for the phy controller.

- interrupts: interrupt values for level interrupt,

	pulse interrupt, special interrupt.

- clocks: from common clock binding: handle to pci clock.

- clock-names: from common clock binding: should be "pcie" and "pcie_bus".

- compatible: should contain "snps,dw-pcie" to identify the core.

- #address-cells: set to <3>

- #size-cells: set to <2>

- device_type: set to "pci"
@@ -19,65 +11,11 @@ Required properties: 
	to define the mapping of the PCIe interface to interrupt

	numbers.

- num-lanes: number of lanes to use

- clocks: Must contain an entry for each entry in clock-names.

	See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

	- "pcie"

	- "pcie_bus"



Optional properties:

- reset-gpio: gpio pin number of power good signal
 


Optional properties for fsl,imx6q-pcie

- power-on-gpio: gpio pin number of power-enable signal

- wake-up-gpio: gpio pin number of incoming wakeup signal

- disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal



Example:



SoC specific DT Entry:



	pcie@290000 {

		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";

		reg = <0x290000 0x1000

			0x270000 0x1000

			0x271000 0x40>;

		interrupts = <0 20 0>, <0 21 0>, <0 22 0>;

		clocks = <&clock 28>, <&clock 27>;

		clock-names = "pcie", "pcie_bus";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */

			  0x81000000 0 0	  0x40001000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0x0 0 &gic 53>;

		num-lanes = <4>;

	};



	pcie@2a0000 {

		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";

		reg = <0x2a0000 0x1000

			0x272000 0x1000

			0x271040 0x40>;

		interrupts = <0 23 0>, <0 24 0>, <0 25 0>;

		clocks = <&clock 29>, <&clock 27>;

		clock-names = "pcie", "pcie_bus";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */

			  0x81000000 0 0	  0x60001000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0x0 0 &gic 56>;

		num-lanes = <4>;

	};



Board specific DT Entry:



	pcie@290000 {

		reset-gpio = <&pin_ctrl 5 0>;

	};



	pcie@2a0000 {

		reset-gpio = <&pin_ctrl 22 0>;

	};

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt

0 → 100644
+38 −0
Original line number Diff line number Diff line 
* Freescale i.MX6 PCIe interface



This PCIe host controller is based on the Synopsis Designware PCIe IP

and thus inherits all the common properties defined in designware-pcie.txt.



Required properties:

- compatible: "fsl,imx6q-pcie"

- reg: base addresse and length of the pcie controller

- interrupts: A list of interrupt outputs of the controller. Must contain an

  entry for each entry in the interrupt-names property.

- interrupt-names: Must include the following entries:

	- "msi": The interrupt that is asserted when an MSI is received

- clock-names: Must include the following additional entries:

	- "pcie_phy"



Example:



	pcie@0x01000000 {

		compatible = "fsl,imx6q-pcie", "snps,dw-pcie";

		reg = <0x01ffc000 0x4000>;

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000

			  0x81000000 0 0          0x01f80000 0 0x00010000

			  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;

		num-lanes = <1>;

		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "msi";

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0x7>;

		interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

		                <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

		                <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

		                <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&clks 144>, <&clks 206>, <&clks 189>;

		clock-names = "pcie", "pcie_bus", "pcie_phy";

	};

Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt

0 → 100644
+65 −0
Original line number Diff line number Diff line 
* Samsung Exynos 5440 PCIe interface



This PCIe host controller is based on the Synopsis Designware PCIe IP

and thus inherits all the common properties defined in designware-pcie.txt.



Required properties:

- compatible: "samsung,exynos5440-pcie"

- reg: base addresses and lengths of the pcie controller,

	the phy controller, additional register for the phy controller.

- interrupts: A list of interrupt outputs for level interrupt,

	pulse interrupt, special interrupt.



Example:



SoC specific DT Entry:



	pcie@290000 {

		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";

		reg = <0x290000 0x1000

			0x270000 0x1000

			0x271000 0x40>;

		interrupts = <0 20 0>, <0 21 0>, <0 22 0>;

		clocks = <&clock 28>, <&clock 27>;

		clock-names = "pcie", "pcie_bus";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */

			  0x81000000 0 0	  0x40001000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

		num-lanes = <4>;

	};



	pcie@2a0000 {

		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";

		reg = <0x2a0000 0x1000

			0x272000 0x1000

			0x271040 0x40>;

		interrupts = <0 23 0>, <0 24 0>, <0 25 0>;

		clocks = <&clock 29>, <&clock 27>;

		clock-names = "pcie", "pcie_bus";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */

			  0x81000000 0 0	  0x60001000 0 0x00010000   /* downstream I/O */

			  0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;

		num-lanes = <4>;

	};



Board specific DT Entry:



	pcie@290000 {

		reset-gpio = <&pin_ctrl 5 0>;

	};



	pcie@2a0000 {

		reset-gpio = <&pin_ctrl 22 0>;

	};

drivers/pci/access.c

+1 −4
Original line number Diff line number Diff line
@@ -231,10 +231,7 @@ static int pci_vpd_pci22_wait(struct pci_dev *dev) 
		}



		if (time_after(jiffies, timeout)) {

			dev_printk(KERN_DEBUG, &dev->dev,

				   "vpd r/w failed.  This is likely a firmware "

				   "bug on this device.  Contact the card "

				   "vendor for a firmware update.");

			dev_printk(KERN_DEBUG, &dev->dev, "vpd r/w failed.  This is likely a firmware bug on this device.  Contact the card vendor for a firmware update\n");

			return -ETIMEDOUT;

		}

		if (fatal_signal_pending(current))

drivers/pci/bus.c

+3 −3
Original line number Diff line number Diff line
@@ -226,6 +226,7 @@ int pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res, 
					 type_mask, alignf, alignf_data,

					 &pci_32_bit);

}

EXPORT_SYMBOL(pci_bus_alloc_resource);



void __weak pcibios_resource_survey_bus(struct pci_bus *bus) { }
@@ -253,6 +254,7 @@ void pci_bus_add_device(struct pci_dev *dev) 


	dev->is_added = 1;

}

EXPORT_SYMBOL_GPL(pci_bus_add_device);



/**

 * pci_bus_add_devices - start driver for PCI devices
@@ -279,6 +281,7 @@ void pci_bus_add_devices(const struct pci_bus *bus) 
			pci_bus_add_devices(child);

	}

}

EXPORT_SYMBOL(pci_bus_add_devices);



/** pci_walk_bus - walk devices on/under bus, calling callback.

 *  @top      bus whose devices should be walked
@@ -344,6 +347,3 @@ void pci_bus_put(struct pci_bus *bus) 
}

EXPORT_SYMBOL(pci_bus_put);

EXPORT_SYMBOL(pci_bus_alloc_resource);

EXPORT_SYMBOL_GPL(pci_bus_add_device);

EXPORT_SYMBOL(pci_bus_add_devices);