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Commit 721a9205 authored by Markos Chandras's avatar Markos Chandras Committed by Ralf Baechle
Browse files

MIPS: Fix typo when reporting cache and ftlb errors for ImgTec cores 



Introduced by the following two commits:
75b5b5e0
"MIPS: Add support for FTLBs"
6de20451
"MIPS: Add printing of ES bit for Imgtec cores when cache error occurs"

Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Reported-by: default avatarMatheus Almeida <Matheus.Almeida@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: stable@vger.kernel.org # v3.14+
Patchwork: https://patchwork.linux-mips.org/patch/6980/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent defb79f0

arch/mips/kernel/traps.c

+2 −2
Original line number Diff line number Diff line
@@ -1545,7 +1545,7 @@ asmlinkage void cache_parity_error(void) 
	       reg_val & (1<<30) ? "secondary" : "primary",

	       reg_val & (1<<31) ? "data" : "insn");

	if (cpu_has_mips_r2 &&

	    ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) {

	    ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {

		pr_err("Error bits: %s%s%s%s%s%s%s%s\n",

			reg_val & (1<<29) ? "ED " : "",

			reg_val & (1<<28) ? "ET " : "",
@@ -1585,7 +1585,7 @@ asmlinkage void do_ftlb(void) 


	/* For the moment, report the problem and hang. */

	if (cpu_has_mips_r2 &&

	    ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) {

	    ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {

		pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",

		       read_c0_ecc());

		pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());