Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 6f9a4894 authored by Sachin Kamat's avatar Sachin Kamat Committed by Mike Turquette
Browse files

Documentation: clk: Fix a trivial typo in audss 



Fixes a trivial typo.

Signed-off-by: default avatarSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent d2127ac4

Documentation/devicetree/bindings/clock/clk-exynos-audss.txt

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 


The Samsung Audio Subsystem clock controller generates and supplies clocks

to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock

binding described here is applicable to all SoC's in Exynos family.

binding described here is applicable to all SoCs in Exynos family.



Required Properties: