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Commit 6d8ea7de authored by Alex Deucher's avatar Alex Deucher
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drm/radeon: fix display tiling setup on SI 

Apply the same logic as CI to SI for setting up the
display tiling parameters.  The num banks may vary
per tiling index just like CI.

Bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=71488
https://bugs.freedesktop.org/show_bug.cgi?id=73946
https://bugs.freedesktop.org/show_bug.cgi?id=74927



Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 78b03510

drivers/gpu/drm/radeon/atombios_crtc.c

+7 −6
Original line number Diff line number Diff line
@@ -1176,7 +1176,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 
		evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);



		/* Set NUM_BANKS. */

		if (rdev->family >= CHIP_BONAIRE) {

		if (rdev->family >= CHIP_TAHITI) {

			unsigned tileb, index, num_banks, tile_split_bytes;



			/* Calculate the macrotile mode index. */
@@ -1194,13 +1194,14 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 
				return -EINVAL;

			}



			if (rdev->family >= CHIP_BONAIRE)

				num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;

			else

				num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;

			fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);

		} else {

			/* SI and older. */

			if (rdev->family >= CHIP_TAHITI)

				tmp = rdev->config.si.tile_config;

			else if (rdev->family >= CHIP_CAYMAN)

			/* NI and older. */

			if (rdev->family >= CHIP_CAYMAN)

				tmp = rdev->config.cayman.tile_config;

			else

				tmp = rdev->config.evergreen.tile_config;