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Commit 6a489c48 authored by David S. Miller's avatar David S. Miller
Browse files


John W. Linville says:

====================
Please pull this batch of fixes intended for the 3.15 stream!

Chun-Yeow Yeoh gives us an ath9k_htc fix so that mac80211 can report
last_tx_rate correctly for those devices..

Fariya Fatima has a number of small fixes for things identified by
the static analysis folks in the new rsi driver.

Felix Fietkau brings an ath9k fix to better support some older chips,
and a fix for a scheduling while atomic bug introduced by an earlier
patch.

Janusz Dziedzic produced an ath9k fix to only enable DFS when a
related build option is selected.

Paul Bolle removes some dead code in rtlwifi.

Rafał Miłecki fixes some b43 code that was accessing some registers
with operations for the wrong register width.

Please let me know if there are problems!
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 45cdf9f3 029d3ac9
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+1 −3
Original line number Diff line number Diff line
@@ -1004,11 +1004,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
	case ATH9K_ANI_FIRSTEP_LEVEL:{
		u32 level = param;

		value = level * 2;
		value = level;
		REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
			      AR_PHY_FIND_SIG_FIRSTEP, value);
		REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
			      AR_PHY_FIND_SIG_FIRSTEP_LOW, value);

		if (level != aniState->firstepLevel) {
			ath_dbg(common, ANI,
+3 −4
Original line number Diff line number Diff line
@@ -312,10 +312,9 @@ static void ath9k_csa_update_vif(void *data, u8 *mac, struct ieee80211_vif *vif)

void ath9k_csa_update(struct ath_softc *sc)
{
	ieee80211_iterate_active_interfaces(sc->hw,
	ieee80211_iterate_active_interfaces_atomic(sc->hw,
						   IEEE80211_IFACE_ITER_NORMAL,
					    ath9k_csa_update_vif,
					    sc);
						   ath9k_csa_update_vif, sc);
}

void ath9k_beacon_tasklet(unsigned long data)
+4 −1
Original line number Diff line number Diff line
@@ -471,8 +471,11 @@ static void ath9k_htc_tx_process(struct ath9k_htc_priv *priv,
	if (!txok || !vif || !txs)
		goto send_mac80211;

	if (txs->ts_flags & ATH9K_HTC_TXSTAT_ACK)
	if (txs->ts_flags & ATH9K_HTC_TXSTAT_ACK) {
		tx_info->flags |= IEEE80211_TX_STAT_ACK;
		if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
			tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
	}

	if (txs->ts_flags & ATH9K_HTC_TXSTAT_FILT)
		tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
+2 −0
Original line number Diff line number Diff line
@@ -670,6 +670,7 @@ static const struct ieee80211_iface_combination if_comb[] = {
		.num_different_channels = 1,
		.beacon_int_infra_match = true,
	},
#ifdef CONFIG_ATH9K_DFS_CERTIFIED
	{
		.limits = if_dfs_limits,
		.n_limits = ARRAY_SIZE(if_dfs_limits),
@@ -679,6 +680,7 @@ static const struct ieee80211_iface_combination if_comb[] = {
		.radar_detect_widths =	BIT(NL80211_CHAN_WIDTH_20_NOHT) |
					BIT(NL80211_CHAN_WIDTH_20),
	}
#endif
};

static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
+7 −7
Original line number Diff line number Diff line
@@ -5176,22 +5176,22 @@ static void b43_nphy_channel_setup(struct b43_wldev *dev,
	int ch = new_channel->hw_value;

	u16 old_band_5ghz;
	u32 tmp32;
	u16 tmp16;

	old_band_5ghz =
		b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
	if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
		tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
		b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
		tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
		b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
		b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
		b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
		b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
		b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
	} else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
		b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
		tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
		b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
		tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
		b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
		b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
		b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
		b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
	}

	b43_chantab_phy_upload(dev, e);
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