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Commit 61ef8be7 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-3.13' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

Radeon fixes, Christmas eve edition.  Fix incorrect family for 0x9649
which lead to bogus rendering, tiling and RB fixes for SI and CIK,
and a UVD fix.

* 'drm-fixes-3.13' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: Bump version for CIK DCE tiling fix
  drm/radeon: set correct number of banks for CIK chips in DCE
  drm/radeon: set correct pipe config for Hawaii in DCE
  drm/radeon: expose render backend mask to the userspace
  drm/radeon: fix render backend setup for SI and CIK
  drm/radeon: 0x9649 is SUMO2 not SUMO
  drm/radeon: fix UVD 256MB check
parents 802eee95 9482d0d3

drivers/gpu/drm/radeon/atombios_crtc.c

+49 −34
Original line number Diff line number Diff line
@@ -1143,9 +1143,32 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 
	}



	if (tiling_flags & RADEON_TILING_MACRO) {

		if (rdev->family >= CHIP_BONAIRE)

			tmp = rdev->config.cik.tile_config;

		else if (rdev->family >= CHIP_TAHITI)

		evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);



		/* Set NUM_BANKS. */

		if (rdev->family >= CHIP_BONAIRE) {

			unsigned tileb, index, num_banks, tile_split_bytes;



			/* Calculate the macrotile mode index. */

			tile_split_bytes = 64 << tile_split;

			tileb = 8 * 8 * target_fb->bits_per_pixel / 8;

			tileb = min(tile_split_bytes, tileb);



			for (index = 0; tileb > 64; index++) {

				tileb >>= 1;

			}



			if (index >= 16) {

				DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",

					  target_fb->bits_per_pixel, tile_split);

				return -EINVAL;

			}



			num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;

			fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);

		} else {

			/* SI and older. */

			if (rdev->family >= CHIP_TAHITI)

				tmp = rdev->config.si.tile_config;

			else if (rdev->family >= CHIP_CAYMAN)

				tmp = rdev->config.cayman.tile_config;
@@ -1164,10 +1187,9 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 
				fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);

				break;

			}

		}



		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);



		evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);

		fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);

		fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);

		fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
@@ -1180,19 +1202,12 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 
		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);



	if (rdev->family >= CHIP_BONAIRE) {

		u32 num_pipe_configs = rdev->config.cik.max_tile_pipes;

		u32 num_rb = rdev->config.cik.max_backends_per_se;

		if (num_pipe_configs > 8)

			num_pipe_configs = 8;

		if (num_pipe_configs == 8)

			fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P8_32x32_16x16);

		else if (num_pipe_configs == 4) {

			if (num_rb == 4)

				fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_16x16);

			else if (num_rb < 4)

				fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_8x16);

		} else if (num_pipe_configs == 2)

			fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P2);

		/* Read the pipe config from the 2D TILED SCANOUT mode.

		 * It should be the same for the other modes too, but not all

		 * modes set the pipe config field. */

		u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;



		fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);

	} else if ((rdev->family == CHIP_TAHITI) ||

		   (rdev->family == CHIP_PITCAIRN))

		fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);

drivers/gpu/drm/radeon/cik.c

+7 −5
Original line number Diff line number Diff line
@@ -3057,7 +3057,7 @@ static u32 cik_create_bitmask(u32 bit_width) 
 * Returns the disabled RB bitmask.

 */

static u32 cik_get_rb_disabled(struct radeon_device *rdev,

			      u32 max_rb_num, u32 se_num,

			      u32 max_rb_num_per_se,

			      u32 sh_per_se)

{

	u32 data, mask;
@@ -3071,7 +3071,7 @@ static u32 cik_get_rb_disabled(struct radeon_device *rdev, 


	data >>= BACKEND_DISABLE_SHIFT;



	mask = cik_create_bitmask(max_rb_num / se_num / sh_per_se);

	mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se);



	return data & mask;

}
@@ -3088,7 +3088,7 @@ static u32 cik_get_rb_disabled(struct radeon_device *rdev, 
 */

static void cik_setup_rb(struct radeon_device *rdev,

			 u32 se_num, u32 sh_per_se,

			 u32 max_rb_num)

			 u32 max_rb_num_per_se)

{

	int i, j;

	u32 data, mask;
@@ -3098,7 +3098,7 @@ static void cik_setup_rb(struct radeon_device *rdev, 
	for (i = 0; i < se_num; i++) {

		for (j = 0; j < sh_per_se; j++) {

			cik_select_se_sh(rdev, i, j);

			data = cik_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);

			data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);

			if (rdev->family == CHIP_HAWAII)

				disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);

			else
@@ -3108,12 +3108,14 @@ static void cik_setup_rb(struct radeon_device *rdev, 
	cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);



	mask = 1;

	for (i = 0; i < max_rb_num; i++) {

	for (i = 0; i < max_rb_num_per_se * se_num; i++) {

		if (!(disabled_rbs & mask))

			enabled_rbs |= mask;

		mask <<= 1;

	}



	rdev->config.cik.backend_enable_mask = enabled_rbs;



	for (i = 0; i < se_num; i++) {

		cik_select_se_sh(rdev, i, 0xffffffff);

		data = 0;

drivers/gpu/drm/radeon/radeon.h

+2 −2
Original line number Diff line number Diff line
@@ -1940,7 +1940,7 @@ struct si_asic { 
	unsigned sc_earlyz_tile_fifo_size;



	unsigned num_tile_pipes;

	unsigned num_backends_per_se;

	unsigned backend_enable_mask;

	unsigned backend_disable_mask_per_asic;

	unsigned backend_map;

	unsigned num_texture_channel_caches;
@@ -1970,7 +1970,7 @@ struct cik_asic { 
	unsigned sc_earlyz_tile_fifo_size;



	unsigned num_tile_pipes;

	unsigned num_backends_per_se;

	unsigned backend_enable_mask;

	unsigned backend_disable_mask_per_asic;

	unsigned backend_map;

	unsigned num_texture_channel_caches;

drivers/gpu/drm/radeon/radeon_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -77,9 +77,10 @@ 
 *   2.33.0 - Add SI tiling mode array query

 *   2.34.0 - Add CIK tiling mode array query

 *   2.35.0 - Add CIK macrotile mode array query

 *   2.36.0 - Fix CIK DCE tiling setup

 */

#define KMS_DRIVER_MAJOR	2

#define KMS_DRIVER_MINOR	35

#define KMS_DRIVER_MINOR	36

#define KMS_DRIVER_PATCHLEVEL	0

int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);

int radeon_driver_unload_kms(struct drm_device *dev);

drivers/gpu/drm/radeon/radeon_kms.c

+9 −0
Original line number Diff line number Diff line
@@ -461,6 +461,15 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 
	case RADEON_INFO_SI_CP_DMA_COMPUTE:

		*value = 1;

		break;

	case RADEON_INFO_SI_BACKEND_ENABLED_MASK:

		if (rdev->family >= CHIP_BONAIRE) {

			*value = rdev->config.cik.backend_enable_mask;

		} else if (rdev->family >= CHIP_TAHITI) {

			*value = rdev->config.si.backend_enable_mask;

		} else {

			DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");

		}

		break;

	default:

		DRM_DEBUG_KMS("Invalid request %d\n", info->request);

		return -EINVAL;