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Commit 5c89a8b6 authored by Boris BREZILLON's avatar Boris BREZILLON Committed by Maxime Ripard
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clk: sunxi: document PRCM clock compatible strings 



Document new compatible strings for clock provided by the PRCM
(Power/Reset/Clock Management) unit.

Signed-off-by: default avatarBoris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: default avatarEmilio López <emilio@elopez.com.ar>
parent c8a76cac

Documentation/devicetree/bindings/clock/sunxi.txt

+3 −0
Original line number Diff line number Diff line
@@ -20,12 +20,15 @@ Required properties: 
	"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13

	"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s

	"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20

	"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31

	"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31

	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31

	"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock

	"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31

	"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10

	"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13

	"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s

	"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31

	"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20

	"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock

	"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing