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Commit 5c11ad95 authored by Joerg Roedel's avatar Joerg Roedel
Browse files

Merge remote-tracking branch 'pci/pri-changes' into x86/amd

parents a06ec394 91f57d5e

Documentation/ABI/testing/sysfs-bus-pci

+18 −0
Original line number Diff line number Diff line
@@ -66,6 +66,24 @@ Description: 
		re-discover previously removed devices.

		Depends on CONFIG_HOTPLUG.



What:		/sys/bus/pci/devices/.../msi_irqs/

Date:		September, 2011

Contact:	Neil Horman <nhorman@tuxdriver.com>

Description:

		The /sys/devices/.../msi_irqs directory contains a variable set

		of sub-directories, with each sub-directory being named after a

		corresponding msi irq vector allocated to that device.  Each

		numbered sub-directory N contains attributes of that irq.

		Note that this directory is not created for device drivers which

		do not support msi irqs



What:		/sys/bus/pci/devices/.../msi_irqs/<N>/mode

Date:		September 2011

Contact:	Neil Horman <nhorman@tuxdriver.com>

Description:

		This attribute indicates the mode that the irq vector named by

		the parent directory is in (msi vs. msix)



What:		/sys/bus/pci/devices/.../remove

Date:		January 2009

Contact:	Linux PCI developers <linux-pci@vger.kernel.org>

drivers/acpi/pci_root.c

+7 −0
Original line number Diff line number Diff line
@@ -596,6 +596,13 @@ static int __devinit acpi_pci_root_add(struct acpi_device *device) 
		if (ACPI_SUCCESS(status)) {

			dev_info(root->bus->bridge,

				"ACPI _OSC control (0x%02x) granted\n", flags);

			if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {

				/*

				 * We have ASPM control, but the FADT indicates

				 * that it's unsupported. Clear it.

				 */

				pcie_clear_aspm(root->bus);

			}

		} else {

			dev_info(root->bus->bridge,

				"ACPI _OSC request failed (%s), "

drivers/pci/ats.c

+45 −45
Original line number Diff line number Diff line
@@ -174,21 +174,22 @@ int pci_enable_pri(struct pci_dev *pdev, u32 reqs) 
	u32 max_requests;

	int pos;



	pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);

	if (!pos)

		return -EINVAL;



	pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);

	pci_read_config_word(pdev, pos + PCI_PRI_STATUS_OFF,  &status);

	if ((control & PCI_PRI_ENABLE) || !(status & PCI_PRI_STATUS_STOPPED))

	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);

	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);

	if ((control & PCI_PRI_CTRL_ENABLE) ||

	    !(status & PCI_PRI_STATUS_STOPPED))

		return -EBUSY;



	pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ_OFF, &max_requests);

	pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);

	reqs = min(max_requests, reqs);

	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ_OFF, reqs);

	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, reqs);



	control |= PCI_PRI_ENABLE;

	pci_write_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, control);

	control |= PCI_PRI_CTRL_ENABLE;

	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);



	return 0;

}
@@ -205,13 +206,13 @@ void pci_disable_pri(struct pci_dev *pdev) 
	u16 control;

	int pos;



	pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);

	if (!pos)

		return;



	pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);

	control &= ~PCI_PRI_ENABLE;

	pci_write_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, control);

	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);

	control &= ~PCI_PRI_CTRL_ENABLE;

	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);

}

EXPORT_SYMBOL_GPL(pci_disable_pri);
@@ -226,13 +227,13 @@ bool pci_pri_enabled(struct pci_dev *pdev) 
	u16 control;

	int pos;



	pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);

	if (!pos)

		return false;



	pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);

	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);



	return (control & PCI_PRI_ENABLE) ? true : false;

	return (control & PCI_PRI_CTRL_ENABLE) ? true : false;

}

EXPORT_SYMBOL_GPL(pci_pri_enabled);
@@ -248,17 +249,17 @@ int pci_reset_pri(struct pci_dev *pdev) 
	u16 control;

	int pos;



	pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);

	if (!pos)

		return -EINVAL;



	pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);

	if (control & PCI_PRI_ENABLE)

	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);

	if (control & PCI_PRI_CTRL_ENABLE)

		return -EBUSY;



	control |= PCI_PRI_RESET;

	control |= PCI_PRI_CTRL_RESET;



	pci_write_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, control);

	pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);



	return 0;

}
@@ -281,14 +282,14 @@ bool pci_pri_stopped(struct pci_dev *pdev) 
	u16 control, status;

	int pos;



	pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);

	if (!pos)

		return true;



	pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);

	pci_read_config_word(pdev, pos + PCI_PRI_STATUS_OFF,  &status);

	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);

	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);



	if (control & PCI_PRI_ENABLE)

	if (control & PCI_PRI_CTRL_ENABLE)

		return false;



	return (status & PCI_PRI_STATUS_STOPPED) ? true : false;
@@ -310,15 +311,15 @@ int pci_pri_status(struct pci_dev *pdev) 
	u16 status, control;

	int pos;



	pos = pci_find_ext_capability(pdev, PCI_PRI_CAP);

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);

	if (!pos)

		return -EINVAL;



	pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control);

	pci_read_config_word(pdev, pos + PCI_PRI_STATUS_OFF,  &status);

	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);

	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);



	/* Stopped bit is undefined when enable == 1, so clear it */

	if (control & PCI_PRI_ENABLE)

	if (control & PCI_PRI_CTRL_ENABLE)

		status &= ~PCI_PRI_STATUS_STOPPED;



	return status;
@@ -341,25 +342,25 @@ int pci_enable_pasid(struct pci_dev *pdev, int features) 
	u16 control, supported;

	int pos;



	pos = pci_find_ext_capability(pdev, PCI_PASID_CAP);

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);

	if (!pos)

		return -EINVAL;



	pci_read_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, &control);

	pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF,     &supported);

	pci_read_config_word(pdev, pos + PCI_PASID_CTRL, &control);

	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);



	if (!(supported & PCI_PASID_ENABLE))

	if (control & PCI_PASID_CTRL_ENABLE)

		return -EINVAL;



	supported &= PCI_PASID_EXEC | PCI_PASID_PRIV;

	supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;



	/* User wants to enable anything unsupported? */

	if ((supported & features) != features)

		return -EINVAL;



	control = PCI_PASID_ENABLE | features;

	control = PCI_PASID_CTRL_ENABLE | features;



	pci_write_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, control);

	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);



	return 0;

}
@@ -375,11 +376,11 @@ void pci_disable_pasid(struct pci_dev *pdev) 
	u16 control = 0;

	int pos;



	pos = pci_find_ext_capability(pdev, PCI_PASID_CAP);

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);

	if (!pos)

		return;



	pci_write_config_word(pdev, pos + PCI_PASID_CONTROL_OFF, control);

	pci_write_config_word(pdev, pos + PCI_PASID_CTRL, control);

}

EXPORT_SYMBOL_GPL(pci_disable_pasid);
@@ -390,22 +391,21 @@ EXPORT_SYMBOL_GPL(pci_disable_pasid); 
 * Returns a negative value when no PASI capability is present.

 * Otherwise is returns a bitmask with supported features. Current

 * features reported are:

 * PCI_PASID_ENABLE - PASID capability can be enabled

 * PCI_PASID_EXEC - Execute permission supported

 * PCI_PASID_PRIV - Priviledged mode supported

 * PCI_PASID_CAP_EXEC - Execute permission supported

 * PCI_PASID_CAP_PRIV - Priviledged mode supported

 */

int pci_pasid_features(struct pci_dev *pdev)

{

	u16 supported;

	int pos;



	pos = pci_find_ext_capability(pdev, PCI_PASID_CAP);

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);

	if (!pos)

		return -EINVAL;



	pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported);

	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);



	supported &= PCI_PASID_ENABLE | PCI_PASID_EXEC | PCI_PASID_PRIV;

	supported &= PCI_PASID_CAP_EXEC | PCI_PASID_CAP_PRIV;



	return supported;

}
@@ -425,11 +425,11 @@ int pci_max_pasids(struct pci_dev *pdev) 
	u16 supported;

	int pos;



	pos = pci_find_ext_capability(pdev, PCI_PASID_CAP);

	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);

	if (!pos)

		return -EINVAL;



	pci_read_config_word(pdev, pos + PCI_PASID_CAP_OFF, &supported);

	pci_read_config_word(pdev, pos + PCI_PASID_CAP, &supported);



	supported = (supported & PASID_NUMBER_MASK) >> PASID_NUMBER_SHIFT;

drivers/pci/hotplug/acpiphp_glue.c

+2 −2
Original line number Diff line number Diff line
@@ -467,7 +467,7 @@ static int add_bridge(acpi_handle handle) 
	 * granted by the BIOS for it.

	 */

	root = acpi_pci_find_root(handle);

	if (root && (root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL))

	if (root && (root->osc_control_set & OSC_PCI_NATIVE_HOTPLUG))

		return -ENODEV;



	/* if the bridge doesn't have _STA, we assume it is always there */
@@ -1395,7 +1395,7 @@ find_root_bridges(acpi_handle handle, u32 lvl, void *context, void **rv) 
	if (!root)

		return AE_OK;



	if (root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)

	if (root->osc_control_set & OSC_PCI_NATIVE_HOTPLUG)

		return AE_OK;



	(*count)++;

drivers/pci/hotplug/pciehp.h

+0 −1
Original line number Diff line number Diff line
@@ -45,7 +45,6 @@ extern int pciehp_poll_time; 
extern int pciehp_debug;

extern int pciehp_force;

extern struct workqueue_struct *pciehp_wq;

extern struct workqueue_struct *pciehp_ordered_wq;



#define dbg(format, arg...)						\

do {									\