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Commit 4d301512 authored by Will Deacon's avatar Will Deacon
Browse files

ARM: perf: clean and update ARMv7 event numbers 



This patch updates the ARMv7 perf event numbers so that:

(1) A consistent naming scheme is used between different CPUs.

(2) Only events actually used by Linux are described.

(3) Where possible, architected events are used in preference to
    CPU-specific events.

This results in the removal of a load of unused, hardcoded data and
makes it more clear as to which events are supported on each PMU.

Cc: Jean Pihet <j-pihet@ti.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 5611cc45

arch/arm/kernel/perf_event_v7.c

+125 −233
Original line number Diff line number Diff line
@@ -29,40 +29,42 @@ static struct arm_pmu armv7pmu; 
 */

enum armv7_perf_types {

	ARMV7_PERFCTR_PMNC_SW_INCR			= 0x00,

	ARMV7_PERFCTR_IFETCH_MISS		= 0x01,

	ARMV7_PERFCTR_ITLB_MISS			= 0x02,

	ARMV7_PERFCTR_DCACHE_REFILL		= 0x03,	/* L1 */

	ARMV7_PERFCTR_DCACHE_ACCESS		= 0x04,	/* L1 */

	ARMV7_PERFCTR_L1_ICACHE_REFILL			= 0x01,

	ARMV7_PERFCTR_ITLB_REFILL			= 0x02,

	ARMV7_PERFCTR_L1_DCACHE_REFILL			= 0x03,

	ARMV7_PERFCTR_L1_DCACHE_ACCESS			= 0x04,

	ARMV7_PERFCTR_DTLB_REFILL			= 0x05,

	ARMV7_PERFCTR_DREAD			= 0x06,

	ARMV7_PERFCTR_DWRITE			= 0x07,

	ARMV7_PERFCTR_MEM_READ				= 0x06,

	ARMV7_PERFCTR_MEM_WRITE				= 0x07,

	ARMV7_PERFCTR_INSTR_EXECUTED			= 0x08,

	ARMV7_PERFCTR_EXC_TAKEN				= 0x09,

	ARMV7_PERFCTR_EXC_EXECUTED			= 0x0A,

	ARMV7_PERFCTR_CID_WRITE				= 0x0B,

	/* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.



	/*

	 * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.

	 * It counts:

	 *  - all branch instructions,

	 *  - all (taken) branch instructions,

	 *  - instructions that explicitly write the PC,

	 *  - exception generating instructions.

	 */

	ARMV7_PERFCTR_PC_WRITE				= 0x0C,

	ARMV7_PERFCTR_PC_IMM_BRANCH			= 0x0D,

	ARMV7_PERFCTR_PC_PROC_RETURN			= 0x0E,

	ARMV7_PERFCTR_UNALIGNED_ACCESS		= 0x0F,



	/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */

	ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS		= 0x0F,

	ARMV7_PERFCTR_PC_BRANCH_MIS_PRED		= 0x10,

	ARMV7_PERFCTR_CLOCK_CYCLES			= 0x11,

	ARMV7_PERFCTR_PC_BRANCH_PRED			= 0x12,



	/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */

	ARMV7_PERFCTR_MEM_ACCESS			= 0x13,

	ARMV7_PERFCTR_L1_ICACHE_ACCESS			= 0x14,

	ARMV7_PERFCTR_L1_DCACHE_WB			= 0x15,

	ARMV7_PERFCTR_L2_DCACHE_ACCESS		= 0x16,

	ARMV7_PERFCTR_L2_DCACHE_REFILL		= 0x17,

	ARMV7_PERFCTR_L2_DCACHE_WB		= 0x18,

	ARMV7_PERFCTR_L2_CACHE_ACCESS			= 0x16,

	ARMV7_PERFCTR_L2_CACHE_REFILL			= 0x17,

	ARMV7_PERFCTR_L2_CACHE_WB			= 0x18,

	ARMV7_PERFCTR_BUS_ACCESS			= 0x19,

	ARMV7_PERFCTR_MEMORY_ERROR		= 0x1A,

	ARMV7_PERFCTR_MEM_ERROR				= 0x1A,

	ARMV7_PERFCTR_INSTR_SPEC			= 0x1B,

	ARMV7_PERFCTR_TTBR_WRITE			= 0x1C,

	ARMV7_PERFCTR_BUS_CYCLES			= 0x1D,
@@ -72,121 +74,38 @@ enum armv7_perf_types { 


/* ARMv7 Cortex-A8 specific event types */

enum armv7_a8_perf_types {

	ARMV7_PERFCTR_WRITE_BUFFER_FULL		= 0x40,

	ARMV7_PERFCTR_L2_STORE_MERGED		= 0x41,

	ARMV7_PERFCTR_L2_STORE_BUFF		= 0x42,

	ARMV7_PERFCTR_L2_ACCESS			= 0x43,

	ARMV7_PERFCTR_L2_CACH_MISS		= 0x44,

	ARMV7_PERFCTR_AXI_READ_CYCLES		= 0x45,

	ARMV7_PERFCTR_AXI_WRITE_CYCLES		= 0x46,

	ARMV7_PERFCTR_MEMORY_REPLAY		= 0x47,

	ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY	= 0x48,

	ARMV7_PERFCTR_L1_DATA_MISS		= 0x49,

	ARMV7_PERFCTR_L1_INST_MISS		= 0x4A,

	ARMV7_PERFCTR_L1_DATA_COLORING		= 0x4B,

	ARMV7_PERFCTR_L1_NEON_DATA		= 0x4C,

	ARMV7_PERFCTR_L1_NEON_CACH_DATA		= 0x4D,

	ARMV7_PERFCTR_L2_NEON			= 0x4E,

	ARMV7_PERFCTR_L2_NEON_HIT		= 0x4F,

	ARMV7_PERFCTR_L1_INST			= 0x50,

	ARMV7_PERFCTR_PC_RETURN_MIS_PRED	= 0x51,

	ARMV7_PERFCTR_PC_BRANCH_FAILED		= 0x52,

	ARMV7_PERFCTR_PC_BRANCH_TAKEN		= 0x53,

	ARMV7_PERFCTR_PC_BRANCH_EXECUTED	= 0x54,

	ARMV7_PERFCTR_OP_EXECUTED		= 0x55,

	ARMV7_PERFCTR_CYCLES_INST_STALL		= 0x56,

	ARMV7_PERFCTR_CYCLES_INST		= 0x57,

	ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL	= 0x58,

	ARMV7_PERFCTR_CYCLES_NEON_INST_STALL	= 0x59,

	ARMV7_PERFCTR_NEON_CYCLES		= 0x5A,



	ARMV7_PERFCTR_PMU0_EVENTS		= 0x70,

	ARMV7_PERFCTR_PMU1_EVENTS		= 0x71,

	ARMV7_PERFCTR_PMU_EVENTS		= 0x72,

	ARMV7_A8_PERFCTR_L2_CACHE_ACCESS		= 0x43,

	ARMV7_A8_PERFCTR_L2_CACHE_REFILL		= 0x44,

	ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS		= 0x50,

};



/* ARMv7 Cortex-A9 specific event types */

enum armv7_a9_perf_types {

	ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC	= 0x40,

	ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC	= 0x41,

	ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC	= 0x42,



	ARMV7_PERFCTR_COHERENT_LINE_MISS	= 0x50,

	ARMV7_PERFCTR_COHERENT_LINE_HIT		= 0x51,



	ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES	= 0x60,

	ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES	= 0x61,

	ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES	= 0x62,

	ARMV7_PERFCTR_STREX_EXECUTED_PASSED	= 0x63,

	ARMV7_PERFCTR_STREX_EXECUTED_FAILED	= 0x64,

	ARMV7_PERFCTR_DATA_EVICTION		= 0x65,

	ARMV7_PERFCTR_ISSUE_STAGE_NO_INST	= 0x66,

	ARMV7_PERFCTR_ISSUE_STAGE_EMPTY		= 0x67,

	ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE	= 0x68,



	ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS	= 0x6E,



	ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST	= 0x70,

	ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST	= 0x71,

	ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST	= 0x72,

	ARMV7_PERFCTR_FP_EXECUTED_INST		= 0x73,

	ARMV7_PERFCTR_NEON_EXECUTED_INST	= 0x74,



	ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES	= 0x80,

	ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES	= 0x81,

	ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES	= 0x82,

	ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES	= 0x83,

	ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES	= 0x84,

	ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES	= 0x85,

	ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES	= 0x86,



	ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES	= 0x8A,

	ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES	= 0x8B,



	ARMV7_PERFCTR_ISB_INST			= 0x90,

	ARMV7_PERFCTR_DSB_INST			= 0x91,

	ARMV7_PERFCTR_DMB_INST			= 0x92,

	ARMV7_PERFCTR_EXT_INTERRUPTS		= 0x93,



	ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED	= 0xA0,

	ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED	= 0xA1,

	ARMV7_PERFCTR_PLE_FIFO_FLUSH		= 0xA2,

	ARMV7_PERFCTR_PLE_RQST_COMPLETED	= 0xA3,

	ARMV7_PERFCTR_PLE_FIFO_OVERFLOW		= 0xA4,

	ARMV7_PERFCTR_PLE_RQST_PROG		= 0xA5

	ARMV7_A9_PERFCTR_INSTR_CORE_RENAME		= 0x68,

};



/* ARMv7 Cortex-A5 specific event types */

enum armv7_a5_perf_types {

	ARMV7_PERFCTR_IRQ_TAKEN			= 0x86,

	ARMV7_PERFCTR_FIQ_TAKEN			= 0x87,



	ARMV7_PERFCTR_EXT_MEM_RQST		= 0xc0,

	ARMV7_PERFCTR_NC_EXT_MEM_RQST		= 0xc1,

	ARMV7_PERFCTR_PREFETCH_LINEFILL		= 0xc2,

	ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP	= 0xc3,

	ARMV7_PERFCTR_ENTER_READ_ALLOC		= 0xc4,

	ARMV7_PERFCTR_READ_ALLOC		= 0xc5,



	ARMV7_PERFCTR_STALL_SB_FULL		= 0xc9,

	ARMV7_A5_PERFCTR_PREFETCH_LINEFILL		= 0xc2,

	ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP		= 0xc3,

};



/* ARMv7 Cortex-A15 specific event types */

enum armv7_a15_perf_types {

	ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS	= 0x40,

	ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS	= 0x41,

	ARMV7_PERFCTR_L1_DCACHE_READ_REFILL	= 0x42,

	ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL	= 0x43,

	ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ		= 0x40,

	ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE	= 0x41,

	ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ		= 0x42,

	ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE	= 0x43,



	ARMV7_PERFCTR_L1_DTLB_READ_REFILL	= 0x4C,

	ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL	= 0x4D,

	ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ		= 0x4C,

	ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE		= 0x4D,



	ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS	= 0x50,

	ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS	= 0x51,

	ARMV7_PERFCTR_L2_DCACHE_READ_REFILL	= 0x52,

	ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL	= 0x53,

	ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ		= 0x50,

	ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE		= 0x51,

	ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ		= 0x52,

	ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE		= 0x53,



	ARMV7_PERFCTR_SPEC_PC_WRITE		= 0x76,

	ARMV7_A15_PERFCTR_PC_WRITE_SPEC			= 0x76,

};



/*
@@ -199,11 +118,11 @@ enum armv7_a15_perf_types { 
static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {

	[PERF_COUNT_HW_CPU_CYCLES]	    = ARMV7_PERFCTR_CPU_CYCLES,

	[PERF_COUNT_HW_INSTRUCTIONS]	    = ARMV7_PERFCTR_INSTR_EXECUTED,

	[PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,

	[PERF_COUNT_HW_CACHE_MISSES]	    = HW_OP_UNSUPPORTED,

	[PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_L1_DCACHE_ACCESS,

	[PERF_COUNT_HW_CACHE_MISSES]	    = ARMV7_PERFCTR_L1_DCACHE_REFILL,

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,

	[PERF_COUNT_HW_BRANCH_MISSES]	    = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

	[PERF_COUNT_HW_BUS_CYCLES]	    = ARMV7_PERFCTR_CLOCK_CYCLES,

	[PERF_COUNT_HW_BUS_CYCLES]	    = HW_OP_UNSUPPORTED,

};



static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -217,12 +136,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
		 * combined.

		 */

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_DCACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_DCACHE_REFILL,

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_DCACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_DCACHE_REFILL,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_DCACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_DCACHE_REFILL,

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_DCACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_DCACHE_REFILL,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
@@ -231,12 +150,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
	},

	[C(L1I)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_INST,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_INST_MISS,

			[C(RESULT_ACCESS)]	= ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_ICACHE_REFILL,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_INST,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_INST_MISS,

			[C(RESULT_ACCESS)]	= ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_ICACHE_REFILL,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
@@ -245,12 +164,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
	},

	[C(LL)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L2_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L2_CACH_MISS,

			[C(RESULT_ACCESS)]	= ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_A8_PERFCTR_L2_CACHE_REFILL,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L2_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L2_CACH_MISS,

			[C(RESULT_ACCESS)]	= ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_A8_PERFCTR_L2_CACHE_REFILL,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
@@ -274,11 +193,11 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
	[C(ITLB)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_REFILL,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_REFILL,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
@@ -287,14 +206,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
	},

	[C(BPU)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_WRITE,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_WRITE,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
@@ -322,13 +239,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
 */

static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {

	[PERF_COUNT_HW_CPU_CYCLES]	    = ARMV7_PERFCTR_CPU_CYCLES,

	[PERF_COUNT_HW_INSTRUCTIONS]	    =

					ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,

	[PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_DCACHE_ACCESS,

	[PERF_COUNT_HW_CACHE_MISSES]	    = ARMV7_PERFCTR_DCACHE_REFILL,

	[PERF_COUNT_HW_INSTRUCTIONS]	    = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME,

	[PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_L1_DCACHE_ACCESS,

	[PERF_COUNT_HW_CACHE_MISSES]	    = ARMV7_PERFCTR_L1_DCACHE_REFILL,

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,

	[PERF_COUNT_HW_BRANCH_MISSES]	    = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

	[PERF_COUNT_HW_BUS_CYCLES]	    = ARMV7_PERFCTR_CLOCK_CYCLES,

	[PERF_COUNT_HW_BUS_CYCLES]	    = HW_OP_UNSUPPORTED,

};



static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -342,12 +258,12 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
		 * combined.

		 */

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_DCACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_DCACHE_REFILL,

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_DCACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_DCACHE_REFILL,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_DCACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_DCACHE_REFILL,

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_DCACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_DCACHE_REFILL,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
@@ -357,11 +273,11 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
	[C(L1I)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_ICACHE_REFILL,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_ICACHE_REFILL,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
@@ -399,11 +315,11 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
	[C(ITLB)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_REFILL,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_REFILL,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
@@ -412,14 +328,12 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
	},

	[C(BPU)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_WRITE,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_WRITE,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
@@ -448,8 +362,8 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = {

	[PERF_COUNT_HW_CPU_CYCLES]	    = ARMV7_PERFCTR_CPU_CYCLES,

	[PERF_COUNT_HW_INSTRUCTIONS]	    = ARMV7_PERFCTR_INSTR_EXECUTED,

	[PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,

	[PERF_COUNT_HW_CACHE_MISSES]	    = HW_OP_UNSUPPORTED,

	[PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_L1_DCACHE_ACCESS,

	[PERF_COUNT_HW_CACHE_MISSES]	    = ARMV7_PERFCTR_L1_DCACHE_REFILL,

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,

	[PERF_COUNT_HW_BRANCH_MISSES]	    = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

	[PERF_COUNT_HW_BUS_CYCLES]	    = HW_OP_UNSUPPORTED,
@@ -460,42 +374,34 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
					[PERF_COUNT_HW_CACHE_RESULT_MAX] = {

	[C(L1D)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]

					= ARMV7_PERFCTR_DCACHE_ACCESS,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_DCACHE_REFILL,

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_DCACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_DCACHE_REFILL,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]

					= ARMV7_PERFCTR_DCACHE_ACCESS,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_DCACHE_REFILL,

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_DCACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_DCACHE_REFILL,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]

					= ARMV7_PERFCTR_PREFETCH_LINEFILL,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,

			[C(RESULT_ACCESS)]	= ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,

			[C(RESULT_MISS)]	= ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,

		},

	},

	[C(L1I)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_ICACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_ICACHE_REFILL,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_ICACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_ICACHE_REFILL,

		},

		/*

		 * The prefetch counters don't differentiate between the I

		 * side and the D side.

		 */

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]

					= ARMV7_PERFCTR_PREFETCH_LINEFILL,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,

			[C(RESULT_ACCESS)]	= ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,

			[C(RESULT_MISS)]	= ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,

		},

	},

	[C(LL)] = {
@@ -529,11 +435,11 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
	[C(ITLB)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_REFILL,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_REFILL,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
@@ -543,13 +449,11 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
	[C(BPU)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
@@ -564,9 +468,9 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = {

	[PERF_COUNT_HW_CPU_CYCLES]	    = ARMV7_PERFCTR_CPU_CYCLES,

	[PERF_COUNT_HW_INSTRUCTIONS]	    = ARMV7_PERFCTR_INSTR_EXECUTED,

	[PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,

	[PERF_COUNT_HW_CACHE_MISSES]	    = HW_OP_UNSUPPORTED,

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_SPEC_PC_WRITE,

	[PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_L1_DCACHE_ACCESS,

	[PERF_COUNT_HW_CACHE_MISSES]	    = ARMV7_PERFCTR_L1_DCACHE_REFILL,

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC,

	[PERF_COUNT_HW_BRANCH_MISSES]	    = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

	[PERF_COUNT_HW_BUS_CYCLES]	    = ARMV7_PERFCTR_BUS_CYCLES,

};
@@ -576,16 +480,12 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
					[PERF_COUNT_HW_CACHE_RESULT_MAX] = {

	[C(L1D)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]

					= ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_L1_DCACHE_READ_REFILL,

			[C(RESULT_ACCESS)]	= ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ,

			[C(RESULT_MISS)]	= ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]

					= ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL,

			[C(RESULT_ACCESS)]	= ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE,

			[C(RESULT_MISS)]	= ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
@@ -601,11 +501,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
		 */

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_ICACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_ICACHE_REFILL,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_L1_ICACHE_ACCESS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_IFETCH_MISS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_L1_ICACHE_REFILL,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
@@ -614,16 +514,12 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
	},

	[C(LL)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]

					= ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_L2_DCACHE_READ_REFILL,

			[C(RESULT_ACCESS)]	= ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ,

			[C(RESULT_MISS)]	= ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]

					= ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL,

			[C(RESULT_ACCESS)]	= ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE,

			[C(RESULT_MISS)]	= ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
@@ -633,13 +529,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
	[C(DTLB)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_L1_DTLB_READ_REFILL,

			[C(RESULT_MISS)]	= ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL,

			[C(RESULT_MISS)]	= ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
@@ -649,11 +543,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
	[C(ITLB)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_REFILL,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_MISS,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_ITLB_REFILL,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
@@ -663,13 +557,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 
	[C(BPU)] = {

		[C(OP_READ)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

		},

		[C(OP_WRITE)] = {

			[C(RESULT_ACCESS)]	= ARMV7_PERFCTR_PC_BRANCH_PRED,

			[C(RESULT_MISS)]

					= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

			[C(RESULT_MISS)]	= ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,

		},

		[C(OP_PREFETCH)] = {

			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,