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Commit 4934540d authored by Sonic Zhang's avatar Sonic Zhang Committed by Bryan Wu
Browse files

Blackfin arch: enable reprogram cclk and sclk for bf518f-ezbrd 



Signed-off-by: default avatarSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent 501674a5

arch/blackfin/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -330,6 +330,11 @@ config MEM_MT48LC32M16A2TG_75 
	depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)

	default y



config MEM_MT48LC32M8A2_75

	bool

	depends on (BFIN518F_EZBRD)

	default y



source "arch/blackfin/mach-bf518/Kconfig"

source "arch/blackfin/mach-bf527/Kconfig"

source "arch/blackfin/mach-bf533/Kconfig"

arch/blackfin/include/asm/mem_init.h

+4 −2
Original line number Diff line number Diff line
@@ -13,7 +13,8 @@ 
    defined(CONFIG_MEM_GENERIC_BOARD) || \

    defined(CONFIG_MEM_MT48LC32M8A2_75) || \

    defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \

    defined(CONFIG_MEM_MT48LC32M16A2TG_75)

    defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \

    defined(CONFIG_MEM_MT48LC32M8A2_75)

#if (CONFIG_SCLK_HZ > 119402985)

#define SDRAM_tRP       TRP_2

#define SDRAM_tRP_num   2
@@ -100,7 +101,8 @@ 
    defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \

    defined(CONFIG_MEM_GENERIC_BOARD) || \

    defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \

    defined(CONFIG_MEM_MT48LC16M16A2TG_75)

    defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \

    defined(CONFIG_MEM_MT48LC32M8A2_75)

  /*SDRAM INFORMATION: */

#define SDRAM_Tref  64		/* Refresh period in milliseconds   */

#define SDRAM_NRA   8192	/* Number of row addresses in SDRAM */