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Commit 3d6e6149 authored by Hans J. Koch's avatar Hans J. Koch Committed by Sascha Hauer
Browse files

mx35: Fix boot ROM hang in internal boot mode 



If a watchdog reset occurs after booting in internal boot mode, the i.MX35
won't boot anymore. The boot ROM code seems to assume that some clocks are
turned on (they are after a power-on reset). This patch turns on the
necessary clocks.

Signed-off-by: default avatarHans J. Koch <hjk@linutronix.de>
Acked-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reported-by: default avatarJohn Ogness <jogness@linutronix.de>
Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
parent ec53fe3d

arch/arm/mach-mx3/clock-imx35.c

+16 −4
Original line number Original line Diff line number Diff line
@@ -485,10 +485,10 @@ static struct clk_lookup lookups[] = { 




int __init mx35_clocks_init()

int __init mx35_clocks_init()

{

{

	unsigned int ll = 0;

	unsigned int cgr2 = 3 << 26, cgr3 = 0;





#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)

#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)

	ll = (3 << 16);

	cgr2 |= 3 << 16;

#endif

#endif





	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
@@ -499,8 +499,20 @@ int __init mx35_clocks_init() 
	__raw_writel((3 << 18), CCM_BASE + CCM_CGR0);

	__raw_writel((3 << 18), CCM_BASE + CCM_CGR0);

	__raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),

	__raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),

			CCM_BASE + CCM_CGR1);

			CCM_BASE + CCM_CGR1);

	__raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2);



	__raw_writel(0, CCM_BASE + CCM_CGR3);

	/*

	 * Check if we came up in internal boot mode. If yes, we need some

	 * extra clocks turned on, otherwise the MX35 boot ROM code will

	 * hang after a watchdog reset.

	 */

	if (!(__raw_readl(CCM_BASE + CCM_RCSR) & (3 << 10))) {

		/* Additionally turn on UART1, SCC, and IIM clocks */

		cgr2 |= 3 << 16 | 3 << 4;

		cgr3 |= 3 << 2;

	}



	__raw_writel(cgr2, CCM_BASE + CCM_CGR2);

	__raw_writel(cgr3, CCM_BASE + CCM_CGR3);





	mxc_timer_init(&gpt_clk,

	mxc_timer_init(&gpt_clk,

			MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);

			MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);