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Commit 32f79a8a authored by Michel Dänzer's avatar Michel Dänzer Committed by Alex Deucher
Browse files

drm/radeon/cik: Add macrotile mode array query 



This is required to properly calculate the tiling parameters
in userspace.

Signed-off-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1ddce27d

drivers/gpu/drm/radeon/cik.c

+3 −0
Original line number Diff line number Diff line
@@ -2427,6 +2427,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				gb_tile_moden = 0;

				break;

			}

			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;

			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);

		}

	} else if (num_pipe_configs == 4) {
@@ -2773,6 +2774,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				gb_tile_moden = 0;

				break;

			}

			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;

			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);

		}

	} else if (num_pipe_configs == 2) {
@@ -2990,6 +2992,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				gb_tile_moden = 0;

				break;

			}

			rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;

			WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);

		}

	} else

drivers/gpu/drm/radeon/radeon.h

+1 −0
Original line number Diff line number Diff line
@@ -1982,6 +1982,7 @@ struct cik_asic { 


	unsigned tile_config;

	uint32_t tile_mode_array[32];

	uint32_t macrotile_mode_array[16];

};



union radeon_asic_config {

drivers/gpu/drm/radeon/radeon_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -76,9 +76,10 @@ 
 *   2.32.0 - new info request for rings working

 *   2.33.0 - Add SI tiling mode array query

 *   2.34.0 - Add CIK tiling mode array query

 *   2.35.0 - Add CIK macrotile mode array query

 */

#define KMS_DRIVER_MAJOR	2

#define KMS_DRIVER_MINOR	34

#define KMS_DRIVER_MINOR	35

#define KMS_DRIVER_PATCHLEVEL	0

int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);

int radeon_driver_unload_kms(struct drm_device *dev);

drivers/gpu/drm/radeon/radeon_kms.c

+9 −0
Original line number Diff line number Diff line
@@ -449,6 +449,15 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 
			return -EINVAL;

		}

		break;

	case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:

		if (rdev->family >= CHIP_BONAIRE) {

			value = rdev->config.cik.macrotile_mode_array;

			value_size = sizeof(uint32_t)*16;

		} else {

			DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");

			return -EINVAL;

		}

		break;

	case RADEON_INFO_SI_CP_DMA_COMPUTE:

		*value = 1;

		break;

include/uapi/drm/radeon_drm.h

+2 −0
Original line number Diff line number Diff line
@@ -981,6 +981,8 @@ struct drm_radeon_cs { 
#define RADEON_INFO_SI_TILE_MODE_ARRAY	0x16

/* query if CP DMA is supported on the compute ring */

#define RADEON_INFO_SI_CP_DMA_COMPUTE	0x17

/* CIK macrotile mode array */

#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY	0x18





struct drm_radeon_info {