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Commit 1a5a954c authored by Russell King's avatar Russell King
Browse files

ARM: l2c: fix register naming 



We have a mixture of different devices with different register layouts,
but we group all the bits together in an opaque mess.  Split them out
into those which are L2C-310 specific and ones which refer to earlier
devices.  Provide full auxiliary control register definitions.

Acked-by: default avatarTony Lindgren <tony@atomide.com>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Acked-by: default avatarShawn Guo <shawn.guo@linaro.org>
Acked-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent a8875a09

arch/arm/include/asm/hardware/cache-l2x0.h

+48 −25
Original line number Original line Diff line number Diff line
@@ -26,8 +26,8 @@ 
#define L2X0_CACHE_TYPE			0x004

#define L2X0_CACHE_TYPE			0x004

#define L2X0_CTRL			0x100

#define L2X0_CTRL			0x100

#define L2X0_AUX_CTRL			0x104

#define L2X0_AUX_CTRL			0x104

#define L2X0_TAG_LATENCY_CTRL		0x108

#define L310_TAG_LATENCY_CTRL		0x108

#define L2X0_DATA_LATENCY_CTRL		0x10C

#define L310_DATA_LATENCY_CTRL		0x10C

#define L2X0_EVENT_CNT_CTRL		0x200

#define L2X0_EVENT_CNT_CTRL		0x200

#define L2X0_EVENT_CNT1_CFG		0x204

#define L2X0_EVENT_CNT1_CFG		0x204

#define L2X0_EVENT_CNT0_CFG		0x208

#define L2X0_EVENT_CNT0_CFG		0x208
@@ -54,16 +54,16 @@ 
#define L2X0_LOCKDOWN_WAY_D_BASE	0x900

#define L2X0_LOCKDOWN_WAY_D_BASE	0x900

#define L2X0_LOCKDOWN_WAY_I_BASE	0x904

#define L2X0_LOCKDOWN_WAY_I_BASE	0x904

#define L2X0_LOCKDOWN_STRIDE		0x08

#define L2X0_LOCKDOWN_STRIDE		0x08

#define L2X0_ADDR_FILTER_START		0xC00

#define L310_ADDR_FILTER_START		0xC00

#define L2X0_ADDR_FILTER_END		0xC04

#define L310_ADDR_FILTER_END		0xC04

#define L2X0_TEST_OPERATION		0xF00

#define L2X0_TEST_OPERATION		0xF00

#define L2X0_LINE_DATA			0xF10

#define L2X0_LINE_DATA			0xF10

#define L2X0_LINE_TAG			0xF30

#define L2X0_LINE_TAG			0xF30

#define L2X0_DEBUG_CTRL			0xF40

#define L2X0_DEBUG_CTRL			0xF40

#define L2X0_PREFETCH_CTRL		0xF60

#define L310_PREFETCH_CTRL		0xF60

#define L2X0_POWER_CTRL			0xF80

#define L310_POWER_CTRL			0xF80

#define   L2X0_DYNAMIC_CLK_GATING_EN	(1 << 1)

#define   L310_DYNAMIC_CLK_GATING_EN	(1 << 1)

#define   L2X0_STNDBY_MODE_EN		(1 << 0)

#define   L310_STNDBY_MODE_EN		(1 << 0)





/* Registers shifts and masks */

/* Registers shifts and masks */

#define L2X0_CACHE_ID_PART_MASK		(0xf << 6)

#define L2X0_CACHE_ID_PART_MASK		(0xf << 6)
@@ -88,29 +88,52 @@ 
#define L310_CACHE_ID_RTL_R3P3		0x09

#define L310_CACHE_ID_RTL_R3P3		0x09





#define L2X0_AUX_CTRL_MASK			0xc0000fff

#define L2X0_AUX_CTRL_MASK			0xc0000fff

/* L2C auxiliary control register - bits common to L2C-210/220/310 */

#define L2C_AUX_CTRL_WAY_SIZE_SHIFT		17

#define L2C_AUX_CTRL_WAY_SIZE_MASK		(7 << 17)

#define L2C_AUX_CTRL_WAY_SIZE(n)		((n) << 17)

#define L2C_AUX_CTRL_EVTMON_ENABLE		BIT(20)

#define L2C_AUX_CTRL_PARITY_ENABLE		BIT(21)

#define L2C_AUX_CTRL_SHARED_OVERRIDE		BIT(22)

/* L2C-210/220 common bits */

#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT	0

#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT	0

#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK	0x7

#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK	(7 << 0)

#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT	3

#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT	3

#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK	(0x7 << 3)

#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK	(7 << 3)

#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT		6

#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT		6

#define L2X0_AUX_CTRL_TAG_LATENCY_MASK		(0x7 << 6)

#define L2X0_AUX_CTRL_TAG_LATENCY_MASK		(7 << 6)

#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT	9

#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT	9

#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK	(0x7 << 9)

#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK	(7 << 9)

#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT	16

#define L2X0_AUX_CTRL_ASSOC_SHIFT		13

#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT		17

#define L2X0_AUX_CTRL_ASSOC_MASK		(15 << 13)

#define L2X0_AUX_CTRL_WAY_SIZE_MASK		(0x7 << 17)

/* L2C-210 specific bits */

#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT	22

#define L210_AUX_CTRL_WRAP_DISABLE		BIT(12)

#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT		26

#define L210_AUX_CTRL_WA_OVERRIDE		BIT(23)

#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT		27

#define L210_AUX_CTRL_EXCLUSIVE_ABORT		BIT(24)

#define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT	28

/* L2C-220 specific bits */

#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT	29

#define L220_AUX_CTRL_EXCLUSIVE_CACHE		BIT(12)

#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT		30

#define L220_AUX_CTRL_FWA_SHIFT			23

#define L220_AUX_CTRL_FWA_MASK			(3 << 23)

#define L220_AUX_CTRL_NS_LOCKDOWN		BIT(26)

#define L220_AUX_CTRL_NS_INT_CTRL		BIT(27)

/* L2C-310 specific bits */

#define L310_AUX_CTRL_FULL_LINE_ZERO		BIT(0)	/* R2P0+ */

#define L310_AUX_CTRL_HIGHPRIO_SO_DEV		BIT(10)	/* R2P0+ */

#define L310_AUX_CTRL_STORE_LIMITATION		BIT(11)	/* R2P0+ */

#define L310_AUX_CTRL_EXCLUSIVE_CACHE		BIT(12)

#define L310_AUX_CTRL_ASSOCIATIVITY_16		BIT(16)

#define L310_AUX_CTRL_CACHE_REPLACE_RR		BIT(25)	/* R2P0+ */

#define L310_AUX_CTRL_NS_LOCKDOWN		BIT(26)

#define L310_AUX_CTRL_NS_INT_CTRL		BIT(27)

#define L310_AUX_CTRL_DATA_PREFETCH		BIT(28)

#define L310_AUX_CTRL_INSTR_PREFETCH		BIT(29)

#define L310_AUX_CTRL_EARLY_BRESP		BIT(30)	/* R2P0+ */





#define L2X0_LATENCY_CTRL_SETUP_SHIFT	0

#define L310_LATENCY_CTRL_SETUP(n)		((n) << 0)

#define L2X0_LATENCY_CTRL_RD_SHIFT	4

#define L310_LATENCY_CTRL_RD(n)			((n) << 4)

#define L2X0_LATENCY_CTRL_WR_SHIFT	8

#define L310_LATENCY_CTRL_WR(n)			((n) << 8)





#define L2X0_ADDR_FILTER_EN		1

#define L310_ADDR_FILTER_EN		1





#define L2X0_CTRL_EN			1

#define L2X0_CTRL_EN			1

arch/arm/mach-cns3xxx/core.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -272,9 +272,9 @@ void __init cns3xxx_l2x0_init(void) 
	 *

	 *

	 * 1 cycle of latency for setup, read and write accesses

	 * 1 cycle of latency for setup, read and write accesses

	 */

	 */

	val = readl(base + L2X0_TAG_LATENCY_CTRL);

	val = readl(base + L310_TAG_LATENCY_CTRL);

	val &= 0xfffff888;

	val &= 0xfffff888;

	writel(val, base + L2X0_TAG_LATENCY_CTRL);

	writel(val, base + L310_TAG_LATENCY_CTRL);





	/*

	/*

	 * Data RAM Control register

	 * Data RAM Control register
@@ -285,9 +285,9 @@ void __init cns3xxx_l2x0_init(void) 
	 *

	 *

	 * 1 cycle of latency for setup, read and write accesses

	 * 1 cycle of latency for setup, read and write accesses

	 */

	 */

	val = readl(base + L2X0_DATA_LATENCY_CTRL);

	val = readl(base + L310_DATA_LATENCY_CTRL);

	val &= 0xfffff888;

	val &= 0xfffff888;

	writel(val, base + L2X0_DATA_LATENCY_CTRL);

	writel(val, base + L310_DATA_LATENCY_CTRL);





	/* 32 KiB, 8-way, parity disable */

	/* 32 KiB, 8-way, parity disable */

	l2x0_init(base, 0x00540000, 0xfe000fff);

	l2x0_init(base, 0x00540000, 0xfe000fff);

arch/arm/mach-exynos/sleep.S

+4 −4
Original line number Original line Diff line number Diff line
@@ -65,13 +65,13 @@ ENTRY(exynos_cpu_resume) 
	ldr	r2, [r0, #L2X0_R_AUX_CTRL]

	ldr	r2, [r0, #L2X0_R_AUX_CTRL]

	str	r2, [r1, #L2X0_AUX_CTRL]

	str	r2, [r1, #L2X0_AUX_CTRL]

	ldr	r2, [r0, #L2X0_R_TAG_LATENCY]

	ldr	r2, [r0, #L2X0_R_TAG_LATENCY]

	str	r2, [r1, #L2X0_TAG_LATENCY_CTRL]

	str	r2, [r1, #L310_TAG_LATENCY_CTRL]

	ldr	r2, [r0, #L2X0_R_DATA_LATENCY]

	ldr	r2, [r0, #L2X0_R_DATA_LATENCY]

	str	r2, [r1, #L2X0_DATA_LATENCY_CTRL]

	str	r2, [r1, #L310_DATA_LATENCY_CTRL]

	ldr	r2, [r0, #L2X0_R_PREFETCH_CTRL]

	ldr	r2, [r0, #L2X0_R_PREFETCH_CTRL]

	str	r2, [r1, #L2X0_PREFETCH_CTRL]

	str	r2, [r1, #L310_PREFETCH_CTRL]

	ldr	r2, [r0, #L2X0_R_PWR_CTRL]

	ldr	r2, [r0, #L2X0_R_PWR_CTRL]

	str	r2, [r1, #L2X0_POWER_CTRL]

	str	r2, [r1, #L310_POWER_CTRL]

	mov	r2, #1

	mov	r2, #1

	str	r2, [r1, #L2X0_CTRL]

	str	r2, [r1, #L2X0_CTRL]

skip_l2_resume:

skip_l2_resume:

arch/arm/mach-imx/system.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -124,7 +124,7 @@ void __init imx_init_l2cache(void) 
	}

	}





	/* Configure the L2 PREFETCH and POWER registers */

	/* Configure the L2 PREFETCH and POWER registers */

	val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);

	val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);

	val |= 0x70800000;

	val |= 0x70800000;

	/*

	/*

	 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0

	 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
@@ -137,9 +137,9 @@ void __init imx_init_l2cache(void) 
	 */

	 */

	if (cpu_is_imx6q())

	if (cpu_is_imx6q())

		val &= ~(1 << 30 | 1 << 23);

		val &= ~(1 << 30 | 1 << 23);

	writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);

	writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);

	val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;

	val = L310_DYNAMIC_CLK_GATING_EN | L310_STNDBY_MODE_EN;

	writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);

	writel_relaxed(val, l2x0_base + L310_POWER_CTRL);





	iounmap(l2x0_base);

	iounmap(l2x0_base);

	of_node_put(np);

	of_node_put(np);

arch/arm/mach-omap2/omap-mpuss-lowpower.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -194,7 +194,7 @@ static void save_l2x0_context(void) 
	if (l2x0_base) {

	if (l2x0_base) {

		val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);

		val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);

		__raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);

		__raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);

		val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);

		val = __raw_readl(l2x0_base + L310_PREFETCH_CTRL);

		__raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);

		__raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);

	}

	}

}

}