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Commit 171c067c authored by Kukjin Kim's avatar Kukjin Kim
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ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5



Actually, the base address of uart is different between EXYNOS4
and EXYNOS5 and this patch enables to support uart for EXYNOS4
and EXYNOS5 SoCs at runtime.

Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent b67545fd
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+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o

# device support

obj-y					+= dev-uart.o
obj-$(CONFIG_ARCH_EXYNOS4)		+= dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o
obj-$(CONFIG_EXYNOS4_DEV_PD)		+= dev-pd.o
+4 −1
Original line number Diff line number Diff line
@@ -477,7 +477,10 @@ static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
	for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
		tcfg->has_fracval = 1;

	s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
	if (soc_is_exynos5250())
		s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
	else
		s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
}

static DEFINE_SPINLOCK(eint_lock);
+78 −0
Original line number Diff line number Diff line
/*
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Base EXYNOS UART resource and device definitions
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>

#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/map.h>

#include <plat/devs.h>

#define EXYNOS_UART_RESOURCE(_series, _nr)	\
static struct resource exynos##_series##_uart##_nr##_resource[] = {	\
	[0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART),	\
	[1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr),	\
};

EXYNOS_UART_RESOURCE(4, 0)
EXYNOS_UART_RESOURCE(4, 1)
EXYNOS_UART_RESOURCE(4, 2)
EXYNOS_UART_RESOURCE(4, 3)

struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
	[0] = {
		.resources	= exynos4_uart0_resource,
		.nr_resources	= ARRAY_SIZE(exynos4_uart0_resource),
	},
	[1] = {
		.resources	= exynos4_uart1_resource,
		.nr_resources	= ARRAY_SIZE(exynos4_uart1_resource),
	},
	[2] = {
		.resources	= exynos4_uart2_resource,
		.nr_resources	= ARRAY_SIZE(exynos4_uart2_resource),
	},
	[3] = {
		.resources	= exynos4_uart3_resource,
		.nr_resources	= ARRAY_SIZE(exynos4_uart3_resource),
	},
};

EXYNOS_UART_RESOURCE(5, 0)
EXYNOS_UART_RESOURCE(5, 1)
EXYNOS_UART_RESOURCE(5, 2)
EXYNOS_UART_RESOURCE(5, 3)

struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
	[0] = {
		.resources	= exynos5_uart0_resource,
		.nr_resources	= ARRAY_SIZE(exynos5_uart0_resource),
	},
	[1] = {
		.resources	= exynos5_uart1_resource,
		.nr_resources	= ARRAY_SIZE(exynos5_uart0_resource),
	},
	[2] = {
		.resources	= exynos5_uart2_resource,
		.nr_resources	= ARRAY_SIZE(exynos5_uart2_resource),
	},
	[3] = {
		.resources	= exynos5_uart3_resource,
		.nr_resources	= ARRAY_SIZE(exynos5_uart3_resource),
	},
};
+7 −2
Original line number Diff line number Diff line
@@ -21,7 +21,12 @@
	 */

	.macro addruart, rp, rv, tmp
		ldr	\rp, = S3C_PA_UART
		mov	\rp, #0x10000000
		ldr	\rp, [\rp, #0x0]
		and	\rp, \rp, #0xf00000
		teq	\rp, #0x500000		@@ EXYNOS5
		ldreq	\rp, =EXYNOS5_PA_UART
		movne	\rp, #EXYNOS4_PA_UART	@@ EXYNOS4
		ldr	\rv, =S3C_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0
		add	\rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
+12 −0
Original line number Diff line number Diff line
@@ -173,4 +173,16 @@
/* Set the default NR_IRQS */
#define NR_IRQS			(IRQ_TIMER_BASE + IRQ_TIMER_COUNT)

#define EXYNOS4_IRQ_UART0		IRQ_SPI(52)
#define EXYNOS4_IRQ_UART1		IRQ_SPI(53)
#define EXYNOS4_IRQ_UART2		IRQ_SPI(54)
#define EXYNOS4_IRQ_UART3		IRQ_SPI(55)
#define EXYNOS4_IRQ_UART4		IRQ_SPI(56)

#define EXYNOS5_IRQ_UART0		IRQ_SPI(51)
#define EXYNOS5_IRQ_UART1		IRQ_SPI(52)
#define EXYNOS5_IRQ_UART2		IRQ_SPI(53)
#define EXYNOS5_IRQ_UART3		IRQ_SPI(54)
#define EXYNOS5_IRQ_UART4		IRQ_SPI(55)

#endif /* __ASM_ARCH_IRQS_H */
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