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Commit 13509c3a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux 

Pull i2c changes from Wolfram Sang:
 - new drivers for exynos5, bcm kona, and st micro
 - bigger overhauls for drivers mxs and rcar
 - typical driver bugfixes, cleanups, improvements
 - got rid of the superfluous 'driver' member in i2c_client struct This
   touches a few drivers in other subsystems.  All acked.

* 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (38 commits)
  i2c: bcm-kona: fix error return code in bcm_kona_i2c_probe()
  i2c: i2c-eg20t: do not print error message in syslog if no ACK received
  i2c: bcm-kona: Introduce Broadcom I2C Driver
  i2c: cbus-gpio: Fix device tree binding
  i2c: wmt: add missing clk_disable_unprepare() on error
  i2c: designware: add new ACPI IDs
  i2c: i801: Add Device IDs for Intel Wildcat Point-LP PCH
  i2c: exynos5: Remove incorrect clk_disable_unprepare
  i2c: i2c-st: Add ST I2C controller
  i2c: exynos5: add High Speed I2C controller driver
  i2c: rcar: fixup rcar type naming
  i2c: scmi: remove some bogus NULL checks
  i2c: sh_mobile & rcar: Enable the driver on all ARM platforms
  i2c: sh_mobile: Convert to clk_prepare/unprepare
  i2c: mux: gpio: use reg value for i2c_add_mux_adapter
  i2c: mux: gpio: use gpio_set_value_cansleep()
  i2c: Include linux/of.h header
  i2c: mxs: Fix PIO mode on i.MX23
  i2c: mxs: Rework the PIO mode operation
  i2c: mxs: distinguish i.MX23 and i.MX28 based I2C controller
  ...
parents 1ea406c0 cfff1f4a

Documentation/devicetree/bindings/i2c/i2c-bcm-kona.txt

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Broadcom Kona Family I2C

=========================



This I2C controller is used in the following Broadcom SoCs:



  BCM11130

  BCM11140

  BCM11351

  BCM28145

  BCM28155



Required Properties

-------------------

- compatible: "brcm,bcm11351-i2c", "brcm,kona-i2c"

- reg: Physical base address and length of controller registers

- interrupts: The interrupt number used by the controller

- clocks: clock specifier for the kona i2c external clock

- clock-frequency: The I2C bus frequency in Hz

- #address-cells: Should be <1>

- #size-cells: Should be <0>



Refer to clocks/clock-bindings.txt for generic clock consumer

properties.



Example:



i2c@3e016000 {

	compatible = "brcm,bcm11351-i2c","brcm,kona-i2c";

	reg = <0x3e016000 0x80>;

	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&bsc1_clk>;

	clock-frequency = <400000>;

	#address-cells = <1>;

	#size-cells = <0>;

};

Documentation/devicetree/bindings/i2c/i2c-exynos5.txt

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* Samsung's High Speed I2C controller



The Samsung's High Speed I2C controller is used to interface with I2C devices

at various speeds ranging from 100khz to 3.4Mhz.



Required properties:

  - compatible: value should be.

      -> "samsung,exynos5-hsi2c", for i2c compatible with exynos5 hsi2c.

  - reg: physical base address of the controller and length of memory mapped

    region.

  - interrupts: interrupt number to the cpu.

  - #address-cells: always 1 (for i2c addresses)

  - #size-cells: always 0



  - Pinctrl:

    - pinctrl-0: Pin control group to be used for this controller.

    - pinctrl-names: Should contain only one value - "default".



Optional properties:

  - clock-frequency: Desired operating frequency in Hz of the bus.

    -> If not specified, the bus operates in fast-speed mode at

       at 100khz.

    -> If specified, the bus operates in high-speed mode only if the

       clock-frequency is >= 1Mhz.



Example:



hsi2c@12ca0000 {

	compatible = "samsung,exynos5-hsi2c";

	reg = <0x12ca0000 0x100>;

	interrupts = <56>;

	clock-frequency = <100000>;



	pinctrl-0 = <&i2c4_bus>;

	pinctrl-names = "default";



	#address-cells = <1>;

	#size-cells = <0>;



	s2mps11_pmic@66 {

		compatible = "samsung,s2mps11-pmic";

		reg = <0x66>;

	};

};

Documentation/devicetree/bindings/i2c/i2c-rcar.txt

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I2C for R-Car platforms



Required properties:

- compatible: Must be one of

	"renesas,i2c-rcar"

	"renesas,i2c-r8a7778"

	"renesas,i2c-r8a7779"

	"renesas,i2c-r8a7790"

- reg: physical base address of the controller and length of memory mapped

  region.

- interrupts: interrupt specifier.



Optional properties:

- clock-frequency: desired I2C bus clock frequency in Hz. The absence of this

  propoerty indicates the default frequency 100 kHz.



Examples :



i2c0: i2c@e6500000 {

	compatible = "renesas,i2c-rcar-h2";

	reg = <0 0xe6500000 0 0x428>;

	interrupts = <0 174 0x4>;

};

Documentation/devicetree/bindings/i2c/i2c-st.txt

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ST SSC binding, for I2C mode operation



Required properties :

- compatible : Must be "st,comms-ssc-i2c" or "st,comms-ssc4-i2c"

- reg : Offset and length of the register set for the device

- interrupts : the interrupt specifier

- clock-names: Must contain "ssc".

- clocks: Must contain an entry for each name in clock-names. See the common

  clock bindings.

- A pinctrl state named "default" must be defined to set pins in mode of

  operation for I2C transfer.



Optional properties :

- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,

  the default 100 kHz frequency will be used. As only Normal and Fast modes

  are supported, possible values are 100000 and 400000.

- st,i2c-min-scl-pulse-width-us : The minimum valid SCL pulse width that is

  allowed through the deglitch circuit. In units of us.

- st,i2c-min-sda-pulse-width-us : The minimum valid SDA pulse width that is

  allowed through the deglitch circuit. In units of us.

- A pinctrl state named "idle" could be defined to set pins in idle state

  when I2C instance is not performing a transfer.

- A pinctrl state named "sleep" could be defined to set pins in sleep state

  when driver enters in suspend.







Example :



i2c0: i2c@fed40000 {

	compatible	= "st,comms-ssc4-i2c";

	reg		= <0xfed40000 0x110>;

	interrupts	=  <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;

	clocks		= <&CLK_S_ICN_REG_0>;

	clock-names	= "ssc";

	clock-frequency = <400000>;

	pinctrl-names	= "default";

	pinctrl-0	= <&pinctrl_i2c0_default>;

	st,i2c-min-scl-pulse-width-us = <0>;

	st,i2c-min-sda-pulse-width-us = <5>;

};

Documentation/i2c/busses/i2c-i801

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@@ -25,6 +25,7 @@ Supported adapters: 
  * Intel Avoton (SOC)

  * Intel Wellsburg (PCH)

  * Intel Coleto Creek (PCH)

  * Intel Wildcat Point-LP (PCH)

   Datasheets: Publicly available at the Intel website



On Intel Patsburg and later chipsets, both the normal host SMBus controller