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Commit 114342f2 authored by Michael Chan's avatar Michael Chan Committed by David S. Miller
Browse files

[TG3]: Fix performance regression on 5705. 



A performance regression was introduced by the following commit:

    commit ee6a99b5
    Author: Michael Chan <mchan@broadcom.com>
    Date:   Wed Jul 18 21:49:10 2007 -0700

    [TG3]: Fix msi issue with kexec/kdump.

In making that change, the PCI latency timer and cache line size
registers were not restored after chip reset.  On the 5705, the
latency timer gets reset to 0 during chip reset and this causes
very poor performance.

Update version to 3.84.

Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent faca94ff

drivers/net/tg3.c

+8 −2
Original line number Diff line number Diff line
@@ -64,8 +64,8 @@ 


#define DRV_MODULE_NAME		"tg3"

#define PFX DRV_MODULE_NAME	": "

#define DRV_MODULE_VERSION	"3.83"

#define DRV_MODULE_RELDATE	"October 10, 2007"

#define DRV_MODULE_VERSION	"3.84"

#define DRV_MODULE_RELDATE	"October 12, 2007"



#define TG3_DEF_MAC_MODE	0

#define TG3_DEF_RX_MODE		0
@@ -5056,6 +5056,12 @@ static void tg3_restore_pci_state(struct tg3 *tp) 


	pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);



	if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {

		pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,

				      tp->pci_cacheline_sz);

		pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,

				      tp->pci_lat_timer);

	}

	/* Make sure PCI-X relaxed ordering bit is clear. */

	if (tp->pcix_cap) {

		u16 pcix_cmd;