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Commit 0b1643b3 authored by Rahul Sharma's avatar Rahul Sharma Committed by Tomasz Figa
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clk/exynos5250: fix bit number for tv sysmmu clock 



Change bit from 2 to 9 for tv (mixer) sysmmu clock.

Signed-off-by: default avatarRahul Sharma <rahul.sharma@samsung.com>
Reviewed-by: default avatarSachin Kamat <sachin.kamat@samsung.com>
Acked-by: default avatarKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
parent a92dda4b

drivers/clk/samsung/clk-exynos5250.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { 
	GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),

	GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),

	GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),

	GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),

	GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",

	GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",

			GATE_IP_DISP1, 2, 0, 0),

			GATE_IP_DISP1, 9, 0, 0),

	GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",

	GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",

			GATE_IP_DISP1, 8, 0, 0),

			GATE_IP_DISP1, 8, 0, 0),

	GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),

	GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),