Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0af3ac1f authored by Avi Kivity's avatar Avi Kivity Committed by Ingo Molnar
Browse files

x86, perf: Add constraints for architectural PMU 



The v1 PMU does not have any fixed counters.  Using the v2 constraints,
which do have fixed counters, causes an additional choice to be present
in the weight calculation, but not when actually scheduling the event,
leading to an event being not scheduled at all.

Signed-off-by: default avatarAvi Kivity <avi@redhat.com>
Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1309362157-6596-3-git-send-email-avi@redhat.com


Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 4dc0da86

arch/x86/kernel/cpu/perf_event_intel.c

+18 −5
Original line number Diff line number Diff line
@@ -112,6 +112,11 @@ static struct extra_reg intel_westmere_extra_regs[] __read_mostly = 
	EVENT_EXTRA_END

};



static struct event_constraint intel_v1_event_constraints[] __read_mostly =

{

	EVENT_CONSTRAINT_END

};



static struct event_constraint intel_gen_event_constraints[] __read_mostly =

{

	FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
@@ -1605,12 +1610,20 @@ static __init int intel_pmu_init(void) 
		pr_cont("SandyBridge events, ");

		break;



	default:

		switch (x86_pmu.version) {

		case 1:

			x86_pmu.event_constraints = intel_v1_event_constraints;

			pr_cont("generic architected perfmon v1, ");

			break;

		default:

			/*

			 * default constraints for v2 and up

			 */

			x86_pmu.event_constraints = intel_gen_event_constraints;

			pr_cont("generic architected perfmon, ");

			break;

		}

	}

	return 0;

}